📄 clocka.rpt
字号:
RESERVED | 19 138 | VCCIO
GND | 20 137 | GND
VCCINT | 21 136 | RESERVED
VCCIO | 22 135 | RESERVED
GND | 23 134 | RESERVED
RESERVED | 24 133 | RESERVED
RESERVED | 25 132 | RESERVED
RESERVED | 26 131 | RESERVED
RESERVED | 27 EP1K30QC208-3 130 | VCCINT
RESERVED | 28 129 | GND
RESERVED | 29 128 | RESERVED
RESERVED | 30 127 | RESERVED
RESERVED | 31 126 | RESERVED
GND | 32 125 | RESERVED
VCCINT | 33 124 | VCCINT
VCCIO | 34 123 | GND
GND | 35 122 | RESERVED
RESERVED | 36 121 | RESERVED
RESERVED | 37 120 | RESERVED
ALARM | 38 119 | RESERVED
RESERVED | 39 118 | VCCIO
RESERVED | 40 117 | GND
RESERVED | 41 116 | RESERVED
VCCIO | 42 115 | RESERVED
GND | 43 114 | RESERVED
RESERVED | 44 113 | RESERVED
ADDSEL0 | 45 112 | RESERVED
ADDSEL1 | 46 111 | RESERVED
ADDSEL2 | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
S S S S S S G S S R R R R V R R R R R V R R R G V G G G G G R V R R R R R R V R R R R R R V R R R R R R
E E E E E E N E E E E E E C E E E E E C E E E N C N N N N N E C E E E E E E C E E E E E E C E E E E E E
C C C C C C D C C S S S S C S S S S S C S S S D C D D D D D S C S S S S S S C S S S S S S C S S S S S S
D D D D D D D D E E E E I E E E E E I E E E I E I E E E E E E I E E E E E E I E E E E E E
I I I I I I I I R R R R O R R R R R N R R R N R O R R R R R R N R R R R R R O R R R R R R
S S S S S S S S V V V V V V V V V T V V V T V V V V V V V T V V V V V V V V V V V V
0 1 2 3 4 5 6 7 E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: d:\zhao\vhdl\neweda\clocka.rpt
clocka
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 2/2 2/2 11/22( 50%)
A2 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 2/2 9/22( 40%)
A4 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 12/22( 54%)
A5 5/ 8( 62%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 9/22( 40%)
A7 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 2/2 6/22( 27%)
A13 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 2/2 11/22( 50%)
A14 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 2/2 1/2 3/22( 13%)
A16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A17 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 1/2 6/22( 27%)
A19 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 11/22( 50%)
A20 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 2/2 10/22( 45%)
A21 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 6/22( 27%)
A22 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
A23 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 4/22( 18%)
A24 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 2/2 2/2 12/22( 54%)
A25 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 17/22( 77%)
A26 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
A27 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 12/22( 54%)
A28 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 12/22( 54%)
A29 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 20/22( 90%)
A30 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
A31 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 6/22( 27%)
A32 7/ 8( 87%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 20/22( 90%)
A33 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 17/22( 77%)
A34 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 20/22( 90%)
A35 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 0/2 13/22( 59%)
A36 5/ 8( 62%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 18/141 ( 12%)
Total logic cells used: 194/1728 ( 11%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.32/4 ( 83%)
Total fan-in: 645/6912 ( 9%)
Total input pins required: 6
Total input I/O cell registers required: 0
Total output pins required: 12
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 194
Total flipflops required: 51
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 48/1728 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 8 8 0 8 5 0 8 0 0 0 0 0 8 8 0 1 8 0 0 8 8 8 8 8 7 8 8 8 8 8 8 2 7 7 8 8 5 194/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 8 8 0 8 5 0 8 0 0 0 0 0 8 8 0 1 8 0 0 8 8 8 8 8 7 8 8 8 8 8 8 2 7 7 8 8 5 194/0
Device-Specific Information: d:\zhao\vhdl\neweda\clocka.rpt
clocka
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
164 - - - 06 INPUT ^ 0 0 0 1 BEGEND
8 - - A -- INPUT ^ 0 0 0 20 CLK
159 - - - 03 INPUT ^ 0 0 0 7 ENTER
162 - - - 05 INPUT ^ 0 0 0 20 KEYUP
163 - - - 06 INPUT ^ 0 0 0 30 RESET
9 - - A -- INPUT ^ 0 0 0 3 SCLK
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\zhao\vhdl\neweda\clocka.rpt
clocka
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
45 - - F -- OUTPUT 0 1 0 0 ADDSEL0
46 - - F -- OUTPUT 0 1 0 0 ADDSEL1
47 - - F -- OUTPUT 0 1 0 0 ADDSEL2
38 - - E -- OUTPUT 0 1 0 0 ALARM
53 - - - 36 OUTPUT 0 1 0 0 SECDIS0
54 - - - 35 OUTPUT 0 1 0 0 SECDIS1
55 - - - 34 OUTPUT 0 1 0 0 SECDIS2
56 - - - 33 OUTPUT 0 1 0 0 SECDIS3
57 - - - 32 OUTPUT 0 1 0 0 SECDIS4
58 - - - 31 OUTPUT 0 1 0 0 SECDIS5
60 - - - 30 OUTPUT 0 1 0 0 SECDIS6
61 - - - 29 OUTPUT 0 0 0 0 SECDIS7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\zhao\vhdl\neweda\clocka.rpt
clocka
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 19 OR2 ! 0 3 0 1 |CLOCK:1|LPM_ADD_SUB:365|addcore:adder|:63
- 8 - A 33 AND2 0 2 0 3 |CLOCK:1|LPM_ADD_SUB:563|addcore:adder|:59
- 7 - A 13 OR2 0 3 0 1 |CLOCK:1|LPM_ADD_SUB:563|addcore:adder|:77
- 2 - A 16 AND2 0 2 0 3 |CLOCK:1|LPM_ADD_SUB:838|addcore:adder|:59
- 8 - A 02 AND2 0 2 0 1 |CLOCK:1|LPM_ADD_SUB:838|addcore:adder|:63
- 7 - A 02 DFFE 1 4 0 11 |CLOCK:1|seclow3 (|CLOCK:1|:43)
- 5 - A 02 DFFE 1 4 0 12 |CLOCK:1|seclow2 (|CLOCK:1|:44)
- 3 - A 02 DFFE 1 4 0 12 |CLOCK:1|seclow1 (|CLOCK:1|:45)
- 2 - A 01 DFFE 1 2 0 11 |CLOCK:1|seclow0 (|CLOCK:1|:46)
- 3 - A 07 DFFE 1 3 0 13 |CLOCK:1|sechigh2 (|CLOCK:1|:47)
- 7 - A 07 DFFE 1 3 0 13 |CLOCK:1|sechigh1 (|CLOCK:1|:48)
- 6 - A 07 DFFE 1 3 0 12 |CLOCK:1|sechigh0 (|CLOCK:1|:49)
- 1 - A 13 DFFE 1 4 0 13 |CLOCK:1|minlow3 (|CLOCK:1|:50)
- 2 - A 13 DFFE 1 4 0 13 |CLOCK:1|minlow2 (|CLOCK:1|:51)
- 8 - A 05 DFFE 1 4 0 12 |CLOCK:1|minlow1 (|CLOCK:1|:52)
- 4 - A 05 DFFE 1 4 0 13 |CLOCK:1|minlow0 (|CLOCK:1|:53)
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