📄 clocka.rpt
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Project Information d:\zhao\vhdl\neweda\clocka.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 11/15/2005 16:46:54
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
clocka EP1K30QC208-3 6 12 0 0 0 % 194 11 %
User Pins: 6 12 0
Project Information d:\zhao\vhdl\neweda\clocka.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
clocka@45 ADDSEL0
clocka@46 ADDSEL1
clocka@47 ADDSEL2
clocka@38 ALARM
clocka@164 BEGEND
clocka@8 CLK
clocka@159 ENTER
clocka@162 KEYUP
clocka@163 RESET
clocka@9 SCLK
clocka@53 SECDIS0
clocka@54 SECDIS1
clocka@55 SECDIS2
clocka@56 SECDIS3
clocka@57 SECDIS4
clocka@58 SECDIS5
clocka@60 SECDIS6
clocka@61 SECDIS7
Project Information d:\zhao\vhdl\neweda\clocka.rpt
** STATE MACHINE ASSIGNMENTS **
|CONTROL:2|adjsta: MACHINE
OF BITS (
|CONTROL:2|adjsta~7,
|CONTROL:2|adjsta~6,
|CONTROL:2|adjsta~5,
|CONTROL:2|adjsta~4,
|CONTROL:2|adjsta~3,
|CONTROL:2|adjsta~2,
|CONTROL:2|adjsta~1
)
WITH STATES (
sethh = B"1000001",
sethl = B"0100001",
setmh = B"0010001",
setml = B"0001001",
setsh = B"0000101",
setsl = B"0000011",
ini = B"0000000"
);
Project Information d:\zhao\vhdl\neweda\clocka.rpt
** FILE HIERARCHY **
|clock:1|
|clock:1|lpm_add_sub:325|
|clock:1|lpm_add_sub:325|addcore:adder|
|clock:1|lpm_add_sub:325|altshift:result_ext_latency_ffs|
|clock:1|lpm_add_sub:325|altshift:carry_ext_latency_ffs|
|clock:1|lpm_add_sub:325|altshift:oflow_ext_latency_ffs|
|clock:1|lpm_add_sub:365|
|clock:1|lpm_add_sub:365|addcore:adder|
|clock:1|lpm_add_sub:365|altshift:result_ext_latency_ffs|
|clock:1|lpm_add_sub:365|altshift:carry_ext_latency_ffs|
|clock:1|lpm_add_sub:365|altshift:oflow_ext_latency_ffs|
|clock:1|lpm_add_sub:463|
|clock:1|lpm_add_sub:463|addcore:adder|
|clock:1|lpm_add_sub:463|altshift:result_ext_latency_ffs|
|clock:1|lpm_add_sub:463|altshift:carry_ext_latency_ffs|
|clock:1|lpm_add_sub:463|altshift:oflow_ext_latency_ffs|
|clock:1|lpm_add_sub:563|
|clock:1|lpm_add_sub:563|addcore:adder|
|clock:1|lpm_add_sub:563|altshift:result_ext_latency_ffs|
|clock:1|lpm_add_sub:563|altshift:carry_ext_latency_ffs|
|clock:1|lpm_add_sub:563|altshift:oflow_ext_latency_ffs|
|clock:1|lpm_add_sub:689|
|clock:1|lpm_add_sub:689|addcore:adder|
|clock:1|lpm_add_sub:689|altshift:result_ext_latency_ffs|
|clock:1|lpm_add_sub:689|altshift:carry_ext_latency_ffs|
|clock:1|lpm_add_sub:689|altshift:oflow_ext_latency_ffs|
|clock:1|lpm_add_sub:838|
|clock:1|lpm_add_sub:838|addcore:adder|
|clock:1|lpm_add_sub:838|altshift:result_ext_latency_ffs|
|clock:1|lpm_add_sub:838|altshift:carry_ext_latency_ffs|
|clock:1|lpm_add_sub:838|altshift:oflow_ext_latency_ffs|
|control:2|
|control:2|lpm_add_sub:223|
|control:2|lpm_add_sub:223|addcore:adder|
|control:2|lpm_add_sub:223|altshift:result_ext_latency_ffs|
|control:2|lpm_add_sub:223|altshift:carry_ext_latency_ffs|
|control:2|lpm_add_sub:223|altshift:oflow_ext_latency_ffs|
|control:2|lpm_add_sub:247|
|control:2|lpm_add_sub:247|addcore:adder|
|control:2|lpm_add_sub:247|altshift:result_ext_latency_ffs|
|control:2|lpm_add_sub:247|altshift:carry_ext_latency_ffs|
|control:2|lpm_add_sub:247|altshift:oflow_ext_latency_ffs|
|control:2|lpm_add_sub:273|
|control:2|lpm_add_sub:273|addcore:adder|
|control:2|lpm_add_sub:273|altshift:result_ext_latency_ffs|
|control:2|lpm_add_sub:273|altshift:carry_ext_latency_ffs|
|control:2|lpm_add_sub:273|altshift:oflow_ext_latency_ffs|
|control:2|lpm_add_sub:300|
|control:2|lpm_add_sub:300|addcore:adder|
|control:2|lpm_add_sub:300|altshift:result_ext_latency_ffs|
|control:2|lpm_add_sub:300|altshift:carry_ext_latency_ffs|
|control:2|lpm_add_sub:300|altshift:oflow_ext_latency_ffs|
|control:2|lpm_add_sub:326|
|control:2|lpm_add_sub:326|addcore:adder|
|control:2|lpm_add_sub:326|altshift:result_ext_latency_ffs|
|control:2|lpm_add_sub:326|altshift:carry_ext_latency_ffs|
|control:2|lpm_add_sub:326|altshift:oflow_ext_latency_ffs|
|control:2|lpm_add_sub:353|
|control:2|lpm_add_sub:353|addcore:adder|
|control:2|lpm_add_sub:353|altshift:result_ext_latency_ffs|
|control:2|lpm_add_sub:353|altshift:carry_ext_latency_ffs|
|control:2|lpm_add_sub:353|altshift:oflow_ext_latency_ffs|
|display:17|
|ring:18|
|ring:18|lpm_mult:172|
|ring:18|lpm_mult:172|multcore:mult_core|
|ring:18|lpm_mult:172|multcore:mult_core|csa_add:padder|
|ring:18|lpm_mult:172|altshift:external_latency_ffs|
|ring:18|lpm_add_sub:185|
|ring:18|lpm_add_sub:185|addcore:adder|
|ring:18|lpm_add_sub:185|altshift:result_ext_latency_ffs|
|ring:18|lpm_add_sub:185|altshift:carry_ext_latency_ffs|
|ring:18|lpm_add_sub:185|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\zhao\vhdl\neweda\clocka.rpt
clocka
***** Logic for device 'clocka' compiled without errors.
Device: EP1K30QC208-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S V S S S S S S S S S S S S S V S S S S S S S S S S S S S B S S S S
E E E E E E E C E E E E E E V E E E E E E E C E E V E E E E E E E E E E E V E R K E E E E E
R R R R R R R C R R R R R R C R R R R R R R C R R C R R R R R R R R R R R C G E E R R N R R
V V V V V V V I V V V V V V C V V V V V G V V I G G G G V V C V V V V V V G V V V V V C E S Y V V T V V
E E E E E E E N E E E E E E I E E E E E N E E N N N N N E E I E E E E E E N E E E E E I N E U E E E E E
D D D D D D D T D D D D D D O D D D D D D D D T D D D D D D O D D D D D D D D D D D D O D T P D D R D D
----------------------------------------------------------------------------------------------------------_
/ 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
#TCK | 1 156 | ^DATA0
^CONF_DONE | 2 155 | ^DCLK
^nCEO | 3 154 | ^nCE
#TDO | 4 153 | #TDI
VCCIO | 5 152 | VCCINT
GND | 6 151 | GND
RESERVED | 7 150 | RESERVED
CLK | 8 149 | RESERVED
SCLK | 9 148 | RESERVED
RESERVED | 10 147 | RESERVED
RESERVED | 11 146 | VCCIO
RESERVED | 12 145 | GND
RESERVED | 13 144 | RESERVED
RESERVED | 14 143 | RESERVED
RESERVED | 15 142 | RESERVED
RESERVED | 16 141 | RESERVED
RESERVED | 17 140 | RESERVED
RESERVED | 18 139 | RESERVED
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