display.vhd

来自「自动打铃系统」· VHDL 代码 · 共 87 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY display IS
PORT(SCLK: IN STD_LOGIC; 
     RESET: IN STD_LOGIC;
     SECDIS: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
     ADDSEL: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
     hourhdis: IN INTEGER RANGE 0 TO 2;
     hourldis,minldis,secldis: in INTEGER RANGE 0 TO 9;
     minhdis,sechdis: IN INTEGER RANGE 0 TO 5);
PROCEDURE LEDDISP(NUMBER:INTEGER RANGE 0 TO 9) IS 
BEGIN 
CASE NUMBER IS
WHEN 0=>
SECDIS<="00111111";
WHEN 1=>
SECDIS<="00000110";
WHEN 2=>
SECDIS<="01011011";
WHEN 3=>
SECDIS<="01001111";
WHEN 4=>
SECDIS<="01100110";
WHEN 5=>
SECDIS<="01101101";
WHEN 6=>
SECDIS<="01111101";
WHEN 7=>
SECDIS<="00000111";
WHEN 8=>
SECDIS<="01111111";
WHEN 9=>
SECDIS<="01101111";
END CASE;
END LEDDISP;
END display;
ARCHITECTURE archi OF display IS
TYPE STATE IS (S1,S2,S3,S4,S5,S6);
SIGNAL NEXSTA:STATE;
SIGNAL CURSTA:STATE;
BEGIN
SCAN:
PROCESS(SCLK)
BEGIN
IF RESET='1' THEN
NEXSTA<=S1;
ELSIF (SCLK='1' AND SCLK'EVENT) THEN
CURSTA<=NEXSTA;
END IF;
CASE CURSTA IS
WHEN S1=>
   ADDSEL<="000";
   LEDDISP(hourhdis);
   NEXSTA<=S2;
WHEN S2=>
   ADDSEL<="001";
   LEDDISP(hourldis);
   NEXSTA<=S3;
WHEN S3=>
   ADDSEL<="010";
   LEDDISP(minhdis);
   NEXSTA<=S4;
WHEN S4=>
   ADDSEL<="011";
   LEDDISP(minldis);
   NEXSTA<=S5;
WHEN S5=>
   ADDSEL<="100";
   LEDDISP(sechdis);
   NEXSTA<=S6;
WHEN S6=>
   ADDSEL<="101";
   LEDDISP(secldis);
   NEXSTA<=S1;
WHEN OTHERS=>
   NULL;
END CASE;
END PROCESS;
END archi;