📄 display.rpt
字号:
- 1 - C 16 OR2 ! 4 0 0 2 :3342
- 2 - C 16 OR2 ! 4 0 0 2 :3354
- 6 - C 16 AND2 4 0 0 6 :3366
- 6 - C 21 OR2 0 3 0 1 :3429
- 6 - C 23 OR2 4 0 0 1 :3482
- 7 - C 23 OR2 0 3 0 1 :3491
- 5 - C 23 OR2 4 0 0 1 :3539
- 1 - C 23 AND2 s 3 0 0 3 ~3549~1
- 3 - C 23 OR2 0 4 0 1 :3549
- 4 - C 23 OR2 4 0 0 2 :3581
- 2 - C 13 AND2 0 3 0 8 :3606
- 7 - C 13 AND2 0 3 0 9 :3616
- 1 - C 13 AND2 0 3 0 17 :3626
- 3 - C 13 OR2 ! 0 3 0 11 :3636
- 8 - C 13 AND2 0 3 0 11 :3646
- 8 - C 19 AND2 0 4 1 0 :3651
- 1 - C 19 OR2 0 4 1 0 :3669
- 4 - C 18 OR2 0 4 0 1 :3709
- 1 - C 15 OR2 s 3 0 0 1 ~3710~1
- 3 - C 16 OR2 s 4 0 0 2 ~3711~1
- 3 - C 18 OR2 s 4 0 0 1 ~3713~1
- 1 - C 22 OR2 3 1 0 1 :3716
- 5 - C 18 OR2 0 4 0 1 :3717
- 8 - C 18 OR2 0 4 0 1 :3718
- 7 - C 18 OR2 s 4 0 0 1 ~3719~1
- 6 - C 18 OR2 1 2 1 0 :3721
- 5 - C 21 OR2 0 4 0 1 :3727
- 7 - C 10 OR2 3 1 0 1 :3734
- 6 - C 10 OR2 0 4 0 1 :3735
- 8 - C 10 OR2 0 4 0 1 :3736
- 4 - C 10 OR2 2 2 1 0 :3739
- 4 - C 16 OR2 s 4 0 0 1 ~3757~1
- 5 - C 16 OR2 s 0 4 0 1 ~3757~2
- 7 - C 16 AND2 s 2 0 0 1 ~3757~3
- 8 - C 16 OR2 s 0 4 0 1 ~3757~4
- 7 - C 14 OR2 s 4 0 0 1 ~3757~5
- 4 - C 20 OR2 s 0 4 0 1 ~3757~6
- 5 - C 20 OR2 s 0 4 0 1 ~3757~7
- 6 - C 20 OR2 s 3 1 0 1 ~3757~8
- 7 - C 20 OR2 s 4 0 0 1 ~3757~9
- 8 - C 20 OR2 s 0 4 0 1 ~3757~10
- 2 - C 20 OR2 s 0 4 0 1 ~3757~11
- 6 - C 15 OR2 1 2 1 0 :3757
- 2 - C 23 OR2 0 4 0 1 :3763
- 3 - C 10 OR2 3 1 0 1 :3770
- 1 - C 10 OR2 0 4 0 1 :3771
- 5 - C 10 OR2 0 4 0 1 :3772
- 2 - C 10 OR2 2 2 1 0 :3775
- 5 - C 15 OR2 0 3 0 1 :3781
- 2 - C 22 OR2 3 1 0 1 :3788
- 7 - C 15 OR2 0 4 0 1 :3789
- 8 - C 15 OR2 0 4 0 1 :3790
- 4 - C 15 OR2 2 2 1 0 :3793
- 4 - C 21 OR2 0 4 0 1 :3799
- 3 - C 19 OR2 3 1 0 1 :3806
- 2 - C 19 OR2 0 4 0 1 :3807
- 4 - C 19 OR2 0 4 0 1 :3808
- 5 - C 19 OR2 0 2 1 0 :3811
- 1 - C 21 OR2 0 4 0 1 :3817
- 4 - C 22 OR2 0 4 0 1 :3820
- 3 - C 22 OR2 0 4 0 1 :3823
- 2 - C 18 OR2 0 4 0 1 :3826
- 2 - C 15 OR2 2 2 1 0 :3829
- 7 - C 19 OR2 0 4 1 1 :3883
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\maxplus2\maxplus2work\display.rpt
display
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 35/ 96( 36%) 2/ 48( 4%) 31/ 48( 64%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus2\maxplus2work\display.rpt
display
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 SCLK
Device-Specific Information: d:\maxplus2\maxplus2work\display.rpt
display
** EQUATIONS **
hourhdis0 : INPUT;
hourhdis1 : INPUT;
hourldis0 : INPUT;
hourldis1 : INPUT;
hourldis2 : INPUT;
hourldis3 : INPUT;
minhdis0 : INPUT;
minhdis1 : INPUT;
minhdis2 : INPUT;
minldis0 : INPUT;
minldis1 : INPUT;
minldis2 : INPUT;
minldis3 : INPUT;
RESET : INPUT;
SCLK : INPUT;
sechdis0 : INPUT;
sechdis1 : INPUT;
sechdis2 : INPUT;
secldis0 : INPUT;
secldis1 : INPUT;
secldis2 : INPUT;
secldis3 : INPUT;
-- Node name is 'ADDSEL0'
-- Equation name is 'ADDSEL0', type is output
ADDSEL0 = !_LC7_C19;
-- Node name is 'ADDSEL1'
-- Equation name is 'ADDSEL1', type is output
ADDSEL1 = _LC1_C19;
-- Node name is 'ADDSEL2'
-- Equation name is 'ADDSEL2', type is output
ADDSEL2 = _LC8_C19;
-- Node name is ':39' = 'CURSTA0'
-- Equation name is 'CURSTA0', location is LC4_C13, type is buried.
CURSTA0 = DFFE( _LC7_C19, GLOBAL( SCLK), VCC, VCC, !_LC2_C11);
-- Node name is ':38' = 'CURSTA1'
-- Equation name is 'CURSTA1', location is LC5_C13, type is buried.
CURSTA1 = DFFE( _EQ001, GLOBAL( SCLK), VCC, VCC, !_LC2_C11);
_EQ001 = _LC3_C13 & !_LC8_C13
# _LC1_C13 & !_LC8_C13;
-- Node name is ':37' = 'CURSTA2'
-- Equation name is 'CURSTA2', location is LC6_C13, type is buried.
CURSTA2 = DFFE( _EQ002, GLOBAL( SCLK), VCC, VCC, !_LC2_C11);
_EQ002 = !CURSTA0 & !CURSTA1 & CURSTA2
# CURSTA0 & CURSTA1 & !CURSTA2;
-- Node name is 'RESET~1'
-- Equation name is 'RESET~1', location is LC2_C11, type is buried.
-- synthesized logic cell
!_LC2_C11 = _LC2_C11~NOT;
_LC2_C11~NOT = LCELL(!RESET);
-- Node name is 'SECDIS0'
-- Equation name is 'SECDIS0', type is output
SECDIS0 = _LC2_C15;
-- Node name is 'SECDIS1'
-- Equation name is 'SECDIS1', type is output
SECDIS1 = _LC5_C19;
-- Node name is 'SECDIS2'
-- Equation name is 'SECDIS2', type is output
SECDIS2 = _LC4_C15;
-- Node name is 'SECDIS3'
-- Equation name is 'SECDIS3', type is output
SECDIS3 = _LC2_C10;
-- Node name is 'SECDIS4'
-- Equation name is 'SECDIS4', type is output
SECDIS4 = _LC6_C15;
-- Node name is 'SECDIS5'
-- Equation name is 'SECDIS5', type is output
SECDIS5 = _LC4_C10;
-- Node name is 'SECDIS6'
-- Equation name is 'SECDIS6', type is output
SECDIS6 = _LC6_C18;
-- Node name is 'SECDIS7'
-- Equation name is 'SECDIS7', type is output
SECDIS7 = GND;
-- Node name is ':1346'
-- Equation name is '_LC3_C20', type is buried
!_LC3_C20 = _LC3_C20~NOT;
_LC3_C20~NOT = LCELL( _EQ003);
_EQ003 = hourldis3
# hourldis0
# !hourldis1
# hourldis2;
-- Node name is ':1358'
-- Equation name is '_LC1_C20', type is buried
!_LC1_C20 = _LC1_C20~NOT;
_LC1_C20~NOT = LCELL( _EQ004);
_EQ004 = hourldis3
# !hourldis0
# hourldis1
# hourldis2;
-- Node name is ':1370'
-- Equation name is '_LC1_C18', type is buried
_LC1_C18 = LCELL( _EQ005);
_EQ005 = !hourldis0 & !hourldis1 & !hourldis2 & !hourldis3;
-- Node name is ':1433'
-- Equation name is '_LC8_C17', type is buried
_LC8_C17 = LCELL( _EQ006);
_EQ006 = hourldis3
# !hourldis1 & hourldis2
# !hourldis0 & !hourldis1
# !hourldis0 & hourldis2;
-- Node name is ':1486'
-- Equation name is '_LC6_C17', type is buried
_LC6_C17 = LCELL( _EQ007);
_EQ007 = hourldis3
# !hourldis2
# hourldis0 & !hourldis1
# !hourldis0 & hourldis1;
-- Node name is ':1493'
-- Equation name is '_LC1_C17', type is buried
_LC1_C17 = LCELL( _EQ008);
_EQ008 = !_LC1_C20 & _LC6_C17
# !_LC1_C20 & _LC2_C17
# _LC1_C18;
-- Node name is ':1543'
-- Equation name is '_LC3_C17', type is buried
_LC3_C17 = LCELL( _EQ009);
_EQ009 = hourldis3
# !hourldis2
# !hourldis0 & !hourldis1
# hourldis0 & hourldis1;
-- Node name is '~1553~1'
-- Equation name is '~1553~1', location is LC2_C17, type is buried.
-- synthesized logic cell
_LC2_C17 = LCELL( _EQ010);
_EQ010 = hourldis1 & !hourldis2 & !hourldis3;
-- Node name is ':1553'
-- Equation name is '_LC4_C17', type is buried
_LC4_C17 = LCELL( _EQ011);
_EQ011 = _LC2_C17
# _LC3_C17
# !_LC5_C17
# _LC1_C18;
-- Node name is ':1585'
-- Equation name is '_LC5_C17', type is buried
_LC5_C17 = LCELL( _EQ012);
_EQ012 = hourldis3
# hourldis1
# hourldis0 & hourldis2
# !hourldis0 & !hourldis2;
-- Node name is ':1859'
-- Equation name is '_LC5_C22', type is buried
_LC5_C22 = LCELL( _EQ013);
_EQ013 = !minhdis0 & !minhdis1 & !minhdis2;
-- Node name is ':2074'
-- Equation name is '_LC6_C22', type is buried
_LC6_C22 = LCELL( _EQ014);
_EQ014 = minhdis1
# !minhdis0 & !minhdis2
# minhdis0 & minhdis2;
-- Node name is ':2344'
-- Equation name is '_LC3_C14', type is buried
!_LC3_C14 = _LC3_C14~NOT;
_LC3_C14~NOT = LCELL( _EQ015);
_EQ015 = minldis3
# minldis0
# !minldis1
# minldis2;
-- Node name is ':2356'
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