ring.vhd

来自「自动打铃系统」· VHDL 代码 · 共 43 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY ring IS
 PORT (reset: IN STD_LOGIC;          
       alarm: OUT STD_LOGIC;
       hourhdis: IN     INTEGER RANGE 0 TO 2;
       hourldis: IN    INTEGER RANGE 0 TO 9;
       minhdis: IN    INTEGER RANGE 0 TO 5;
       minldis: IN    INTEGER RANGE 0 TO 9;
       sechdis: IN     INTEGER RANGE 0 TO 5;
       secldis: IN     INTEGER RANGE 0 TO 9);
 END ring;
 ARCHITECTURE archi OF ring IS
   CONSTANT RT:INTEGER:=5;
   CONSTANT STOP:INTEGER:=2;
BEGIN
PROCESS(secldis)
VARIABLE cnt:INTEGER;
BEGIN
cnt:=sechdis*10+secldis;
IF reset='1' THEN 
alarm<='0';
elsif (hourhdis=0 and hourldis=0 and minhdis=0 and minldis=1 and sechdis<2) OR 
(minhdis=3 and minldis=0 and sechdis<2) OR 
(hourhdis=1 and hourldis=0 and minhdis=3 and minldis=0 and sechdis<2) THEN 
IF cnt<RT then 
alarm<='1';
elsif cnt>=RT and cnt<RT+STOP THEN
alarm<='0';
elsif cnt<2*RT+STOP THEN 
alarm<='1';
else alarm<='0';
end if;
end if;
end PROCESS;
END archi;