az.rpt

服务器的的板在载控制器的AHDL程序,包括原理图编译,用在EPM7128上(CPLD).

+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                 d:\digital\az.rpt
az

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (38)    20    B       SOFT      t        0      0   0    0    2    1    0  |BLOCK1:5|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node1
 (32)    25    B       SOFT      t        0      0   0    0    3    1    0  |BLOCK1:5|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node2
 (33)    24    B       SOFT      t        0      0   0    0    4    1    0  |BLOCK1:5|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node3
 (34)    23    B       SOFT      t        0      0   0    0    5    1    0  |BLOCK1:5|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node4


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                 d:\digital\az.rpt
az

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                           Logic cells placed in LAB 'B'
        +----------------- LC20 |BLOCK1:5|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node1
        | +--------------- LC25 |BLOCK1:5|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node2
        | | +------------- LC24 |BLOCK1:5|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node3
        | | | +----------- LC23 |BLOCK1:5|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node4
        | | | | +--------- LC17 b0
        | | | | | +------- LC18 b1
        | | | | | | +----- LC21 b2
        | | | | | | | +--- LC22 b3
        | | | | | | | | +- LC19 b4
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC20 -> - - - - - * - - - | - * | <-- |BLOCK1:5|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node1
LC25 -> - - - - - - * - - | - * | <-- |BLOCK1:5|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node2
LC24 -> - - - - - - - * - | - * | <-- |BLOCK1:5|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node3
LC23 -> - - - - - - - - * | - * | <-- |BLOCK1:5|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node4
LC17 -> * * * * * * * * * | - * | <-- b0
LC18 -> * * * * - * * * * | - * | <-- b1
LC21 -> - * * * - * * * * | - * | <-- b2
LC22 -> - - * * - * * * * | - * | <-- b3
LC19 -> - - - * - * * * * | - * | <-- b4

Pin
43   -> - - - - - - - - - | - - | <-- in


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                 d:\digital\az.rpt
az

** EQUATIONS **

in       : INPUT;

-- Node name is 'b0' = '|BLOCK1:5|:10' 
-- Equation name is 'b0', type is output 
 b0      = TFFE( VCC, GLOBAL(!in),  VCC,  VCC,  VCC);

-- Node name is 'b1' = '|BLOCK1:5|:8' 
-- Equation name is 'b1', type is output 
 b1      = DFFE( _EQ001 $  _LC020, GLOBAL(!in),  VCC,  VCC,  VCC);
  _EQ001 =  b0 & !b1 &  b2 &  b3 & !b4 &  _LC020;

-- Node name is 'b2' = '|BLOCK1:5|:6' 
-- Equation name is 'b2', type is output 
 b2      = DFFE( _EQ002 $  _LC025, GLOBAL(!in),  VCC,  VCC,  VCC);
  _EQ002 =  b0 & !b1 &  b2 &  b3 & !b4 &  _LC025;

-- Node name is 'b3' = '|BLOCK1:5|:4' 
-- Equation name is 'b3', type is output 
 b3      = DFFE( _EQ003 $  _LC024, GLOBAL(!in),  VCC,  VCC,  VCC);
  _EQ003 =  b0 & !b1 &  b2 &  b3 & !b4 &  _LC024;

-- Node name is 'b4' = '|BLOCK1:5|:2' 
-- Equation name is 'b4', type is output 
 b4      = DFFE( _EQ004 $  _LC023, GLOBAL(!in),  VCC,  VCC,  VCC);
  _EQ004 =  b0 & !b1 &  b2 &  b3 & !b4 &  _LC023;

-- Node name is '|BLOCK1:5|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried 
_LC020   = LCELL( b1 $  b0);

-- Node name is '|BLOCK1:5|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( b2 $  _EQ005);
  _EQ005 =  b0 &  b1;

-- Node name is '|BLOCK1:5|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried 
_LC024   = LCELL( b3 $  _EQ006);
  _EQ006 =  b0 &  b1 &  b2;

-- Node name is '|BLOCK1:5|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried 
_LC023   = LCELL( b4 $  _EQ007);
  _EQ007 =  b0 &  b1 &  b2 &  b3;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                          d:\digital\az.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 2,923K