kvmf.hif

服务器的的板在载控制器的AHDL程序,包括原理图编译,用在EPM7128上(CPLD).

HIF003
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- Warning: do not edit this file!
--
FILES
{
	74138.gdf
	{
		74138 [] []
		{
			4 [] [];
		}
	}
	8_1.gdf
	{
		8_1 [] []
		{
			7 [] [];
		}
	}
	8_6.gdf
	{
		8_6 [] []
		{
			6 [] [];
		}
	}
	muxlut.tdf
	{
		muxlut [CASCADE_CHAIN,LOCAL=0,REM_LATENCY,LATENCY,TOT_LEVELS,LEVEL,SIZE,USE_LPM_FOR_AHDL_OPERATORS] [muxlut.inc,altshift.inc];
	}
	altshift.tdf
	{
		altshift [DEPTH=0,WIDTH=4,USE_LPM_FOR_AHDL_OPERATORS] [];
	}
	bypassff.tdf
	{
		bypassff [WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS] [];
	}
	l_addr_code.tdf
	{
		l_addr_code [USE_LPM_FOR_AHDL_OPERATORS] []
		{
			5 [USE_LPM_FOR_AHDL_OPERATORS=OFF] [FPGA_SEL_N,RAM_SEL_N,RESET_N,SEL1_N,SEL0_N,addr15,addr0,addr1,addr2,addr3,addr4,addr5,addr6];
		}
	}
	lpm_mux.tdf
	{
		lpm_mux [LPM_PIPELINE=0,LPM_WIDTHS,LPM_SIZE,LPM_WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [muxlut.inc,bypassff.inc,altshift.inc];
	}
	74373.gdf
	{
		74373 [] []
		{
			1 [] [];
		}
	}
	delay.gdf
	{
		delay [] []
		{
			2 [] [];
		}
	}
	addr38.gdf
	{
		addr38 [] []
		{
			3 [] [];
		}
	}
	kvmf.gdf
	{
		kvmf [] []
		{
			0 [] [];
		}
	}
}
TREE
{
	kvmf::(0,0):(0): kvmf.gdf
	{
		74373:1:(0,0):(296): 74373.gdf;
		74373:1:(0,0):(588): 74373.gdf;
		74373:1:(0,0):(307): 74373.gdf;
		74373:1:(0,0):(387): 74373.gdf;
		74373:1:(0,0):(408): 74373.gdf;
		delay:2:(0,0):(513): delay.gdf;
		delay:2:(0,0):(508): delay.gdf;
		delay:2:(0,0):(507): delay.gdf;
		delay:2:(0,0):(509): delay.gdf;
		delay:2:(0,0):(511): delay.gdf;
		delay:2:(0,0):(510): delay.gdf;
		delay:2:(0,0):(503): delay.gdf;
		delay:2:(0,0):(506): delay.gdf;
		delay:2:(0,0):(505): delay.gdf;
		delay:2:(0,0):(202): delay.gdf;
		delay:2:(0,0):(243): delay.gdf;
		delay:2:(0,0):(200): delay.gdf;
		delay:2:(0,0):(501): delay.gdf;
		delay:2:(0,0):(500): delay.gdf;
		delay:2:(0,0):(502): delay.gdf;
		delay:2:(0,0):(201): delay.gdf;
		delay:2:(0,0):(499): delay.gdf;
		delay:2:(0,0):(485): delay.gdf;
		delay:2:(0,0):(486): delay.gdf;
		delay:2:(0,0):(484): delay.gdf;
		delay:2:(0,0):(497): delay.gdf;
		delay:2:(0,0):(498): delay.gdf;
		delay:2:(0,0):(487): delay.gdf;
		delay:2:(0,0):(488): delay.gdf;
		delay:2:(0,0):(494): delay.gdf;
		delay:2:(0,0):(495): delay.gdf;
		delay:2:(0,0):(496): delay.gdf;
		delay:2:(0,0):(491): delay.gdf;
		delay:2:(0,0):(489): delay.gdf;
		delay:2:(0,0):(490): delay.gdf;
		delay:2:(0,0):(493): delay.gdf;
		delay:2:(0,0):(492): delay.gdf;
		addr38:3:(0,0):(304): addr38.gdf
		{
			74138:4:(0,0):(4): 74138.gdf;
		}
		l_addr_code:5:(0,0):(516): l_addr_code.tdf;
		8_6:6:(0,0):(564): 8_6.gdf
		{
			8_1:7:(0,0):(29): 8_1.gdf;
			8_1:7:(0,0):(28): 8_1.gdf;
			8_1:7:(0,0):(27): 8_1.gdf;
			8_1:7:(0,0):(26): 8_1.gdf;
			8_1:7:(0,0):(25): 8_1.gdf;
			8_1:7:(0,0):(24): 8_1.gdf;
			addr38:3:(0,0):(30): addr38.gdf
			{
				74138:4:(0,0):(4): 74138.gdf;
			}
		}
	}
}