📄 8_6.rpt
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5 -> - - * - | - - * - | <-- d36
4 -> - - - * | - - * - | <-- d37
70 -> * - - - | - - * - | <-- d43
50 -> - * - - | - - * - | <-- d44
64 -> - - * - | - - * - | <-- d46
69 -> - - - * | - - * - | <-- d47
36 -> * - - - | - - * - | <-- d53
34 -> - * - - | - - * - | <-- d54
29 -> - - * - | - - * - | <-- d56
28 -> - - - * | - - * - | <-- d57
LC52 -> * - - - | - - * - | <-- ~13~4~1~3~2
LC19 -> - * - - | - - * - | <-- ~13~5~1~3~2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\cpld_1112\digital_0111\8_6.rpt
8_6
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------------- LC58 outdata0
| +--------------- LC61 outdata1
| | +------------- LC63 outdata2
| | | +----------- LC60 outdata5
| | | | +--------- LC49 outdata7~1
| | | | | +------- LC62 ~13~1~1~3~2
| | | | | | +----- LC50 ~13~2~1~3~2
| | | | | | | +--- LC53 ~13~3~1~3~2
| | | | | | | | +- LC52 ~13~4~1~3~2
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC62 -> * - - - - - - - - | - - - * | <-- ~13~1~1~3~2
LC50 -> - * - - - - - - - | - - - * | <-- ~13~2~1~3~2
LC53 -> - - * - - - - - - | - - - * | <-- ~13~3~1~3~2
Pin
22 -> * * * * - * * * * | - * * * | <-- addr0
21 -> * * * * * * * * * | - * * * | <-- addr1
20 -> * * * * * * * * * | - * * * | <-- addr2
49 -> - - - - - * - - - | - - - * | <-- d00
24 -> - - - - - - * - - | - - - * | <-- d01
54 -> - - - - - - - * - | - - - * | <-- d02
63 -> - - - - - - - - * | - - - * | <-- d03
73 -> - - - * - - - - - | - - - * | <-- d05
58 -> - - - - - * - - - | - - - * | <-- d10
56 -> - - - - - - * - - | - - - * | <-- d11
51 -> - - - - - - - * - | - - - * | <-- d12
79 -> - - - - - - - - * | - - - * | <-- d13
75 -> - - - * - - - - - | - - - * | <-- d15
57 -> * - - - - - - - - | - - - * | <-- d20
55 -> - * - - - - - - - | - - - * | <-- d21
27 -> - - * - - - - - - | - - - * | <-- d22
12 -> - - - * - - - - - | - - - * | <-- d25
17 -> * - - - - - - - - | - - - * | <-- d30
18 -> - * - - - - - - - | - - - * | <-- d31
10 -> - - * - - - - - - | - - - * | <-- d32
6 -> - - - * - - - - - | - - - * | <-- d35
40 -> * - - - - - - - - | - - - * | <-- d40
35 -> - * - - - - - - - | - - - * | <-- d41
31 -> - - * - - - - - - | - - - * | <-- d42
25 -> - - - * - - - - - | - - - * | <-- d45
41 -> * - - - - - - - - | - - - * | <-- d50
39 -> - * - - - - - - - | - - - * | <-- d51
37 -> - - * - - - - - - | - - - * | <-- d52
33 -> - - - * - - - - - | - - - * | <-- d55
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\cpld_1112\digital_0111\8_6.rpt
8_6
** EQUATIONS **
addr0 : INPUT;
addr1 : INPUT;
addr2 : INPUT;
d00 : INPUT;
d01 : INPUT;
d02 : INPUT;
d03 : INPUT;
d04 : INPUT;
d05 : INPUT;
d06 : INPUT;
d07 : INPUT;
d10 : INPUT;
d11 : INPUT;
d12 : INPUT;
d13 : INPUT;
d14 : INPUT;
d15 : INPUT;
d16 : INPUT;
d17 : INPUT;
d20 : INPUT;
d21 : INPUT;
d22 : INPUT;
d23 : INPUT;
d24 : INPUT;
d25 : INPUT;
d26 : INPUT;
d27 : INPUT;
d30 : INPUT;
d31 : INPUT;
d32 : INPUT;
d33 : INPUT;
d34 : INPUT;
d35 : INPUT;
d36 : INPUT;
d37 : INPUT;
d40 : INPUT;
d41 : INPUT;
d42 : INPUT;
d43 : INPUT;
d44 : INPUT;
d45 : INPUT;
d46 : INPUT;
d47 : INPUT;
d50 : INPUT;
d51 : INPUT;
d52 : INPUT;
d53 : INPUT;
d54 : INPUT;
d55 : INPUT;
d56 : INPUT;
d57 : INPUT;
-- Node name is 'outdata0'
-- Equation name is 'outdata0', location is LC058, type is output.
outdata0 = TRI(_LC058, _LC049);
_LC058 = LCELL( _EQ001 $ !_LC062);
_EQ001 = addr0 & addr1 & !addr2 & !d30 & !_LC062
# addr0 & !addr1 & addr2 & !d50 & !_LC062
# !addr0 & !addr1 & addr2 & !d40 & !_LC062
# !addr0 & addr1 & !addr2 & !d20 & !_LC062;
-- Node name is 'outdata1'
-- Equation name is 'outdata1', location is LC061, type is output.
outdata1 = TRI(_LC061, _LC049);
_LC061 = LCELL( _EQ002 $ !_LC050);
_EQ002 = addr0 & addr1 & !addr2 & !d31 & !_LC050
# addr0 & !addr1 & addr2 & !d51 & !_LC050
# !addr0 & !addr1 & addr2 & !d41 & !_LC050
# !addr0 & addr1 & !addr2 & !d21 & !_LC050;
-- Node name is 'outdata2'
-- Equation name is 'outdata2', location is LC063, type is output.
outdata2 = TRI(_LC063, _LC049);
_LC063 = LCELL( _EQ003 $ !_LC053);
_EQ003 = addr0 & addr1 & !addr2 & !d32 & !_LC053
# addr0 & !addr1 & addr2 & !d52 & !_LC053
# !addr0 & !addr1 & addr2 & !d42 & !_LC053
# !addr0 & addr1 & !addr2 & !d22 & !_LC053;
-- Node name is 'outdata3'
-- Equation name is 'outdata3', location is LC035, type is output.
outdata3 = TRI(_LC035, _LC049);
_LC035 = LCELL( _EQ004 $ !_LC052);
_EQ004 = addr0 & addr1 & !addr2 & !d33 & !_LC052
# addr0 & !addr1 & addr2 & !d53 & !_LC052
# !addr0 & !addr1 & addr2 & !d43 & !_LC052
# !addr0 & addr1 & !addr2 & !d23 & !_LC052;
-- Node name is 'outdata4'
-- Equation name is 'outdata4', location is LC036, type is output.
outdata4 = TRI(_LC036, _LC049);
_LC036 = LCELL( _EQ005 $ !_LC019);
_EQ005 = addr0 & addr1 & !addr2 & !d34 & !_LC019
# addr0 & !addr1 & addr2 & !d54 & !_LC019
# !addr0 & !addr1 & addr2 & !d44 & !_LC019
# !addr0 & addr1 & !addr2 & !d24 & !_LC019;
-- Node name is 'outdata5'
-- Equation name is 'outdata5', location is LC060, type is output.
outdata5 = TRI(_LC060, _LC049);
_LC060 = LCELL( _EQ006 $ _EQ007);
_EQ006 = addr0 & addr1 & !addr2 & !d35 & _X001 & _X002
# addr0 & !addr1 & addr2 & !d55 & _X001 & _X002
# !addr0 & !addr1 & addr2 & !d45 & _X001 & _X002
# !addr0 & addr1 & !addr2 & !d25 & _X001 & _X002;
_X001 = EXP(!addr0 & !addr1 & !addr2 & !d05);
_X002 = EXP( addr0 & !addr1 & !addr2 & !d15);
_EQ007 = _X001 & _X002;
_X001 = EXP(!addr0 & !addr1 & !addr2 & !d05);
_X002 = EXP( addr0 & !addr1 & !addr2 & !d15);
-- Node name is 'outdata6'
-- Equation name is 'outdata6', location is LC034, type is output.
outdata6 = TRI(_LC034, _LC049);
_LC034 = LCELL( _EQ008 $ _EQ009);
_EQ008 = addr0 & addr1 & !addr2 & !d36 & _X003 & _X004
# addr0 & !addr1 & addr2 & !d56 & _X003 & _X004
# !addr0 & !addr1 & addr2 & !d46 & _X003 & _X004
# !addr0 & addr1 & !addr2 & !d26 & _X003 & _X004;
_X003 = EXP(!addr0 & !addr1 & !addr2 & !d06);
_X004 = EXP( addr0 & !addr1 & !addr2 & !d16);
_EQ009 = _X003 & _X004;
_X003 = EXP(!addr0 & !addr1 & !addr2 & !d06);
_X004 = EXP( addr0 & !addr1 & !addr2 & !d16);
-- Node name is 'outdata7~1'
-- Equation name is 'outdata7~1', location is LC049, type is buried.
-- synthesized logic cell
_LC049 = LCELL( _EQ010 $ VCC);
_EQ010 = addr1 & addr2;
-- Node name is 'outdata7'
-- Equation name is 'outdata7', location is LC033, type is output.
outdata7 = TRI(_LC033, _LC049);
_LC033 = LCELL( _EQ011 $ _EQ012);
_EQ011 = addr0 & addr1 & !addr2 & !d37 & _X005 & _X006
# addr0 & !addr1 & addr2 & !d57 & _X005 & _X006
# !addr0 & !addr1 & addr2 & !d47 & _X005 & _X006
# !addr0 & addr1 & !addr2 & !d27 & _X005 & _X006;
_X005 = EXP(!addr0 & !addr1 & !addr2 & !d07);
_X006 = EXP( addr0 & !addr1 & !addr2 & !d17);
_EQ012 = _X005 & _X006;
_X005 = EXP(!addr0 & !addr1 & !addr2 & !d07);
_X006 = EXP( addr0 & !addr1 & !addr2 & !d17);
-- Node name is '~13~1~1~3~2'
-- Equation name is '~13~1~1~3~2', location is LC062, type is buried.
-- synthesized logic cell
_LC062 = LCELL( _EQ013 $ GND);
_EQ013 = addr0 & !addr1 & !addr2 & !d10
# !addr0 & !addr1 & !addr2 & !d00;
-- Node name is '~13~2~1~3~2'
-- Equation name is '~13~2~1~3~2', location is LC050, type is buried.
-- synthesized logic cell
_LC050 = LCELL( _EQ014 $ GND);
_EQ014 = addr0 & !addr1 & !addr2 & !d11
# !addr0 & !addr1 & !addr2 & !d01;
-- Node name is '~13~3~1~3~2'
-- Equation name is '~13~3~1~3~2', location is LC053, type is buried.
-- synthesized logic cell
_LC053 = LCELL( _EQ015 $ GND);
_EQ015 = addr0 & !addr1 & !addr2 & !d12
# !addr0 & !addr1 & !addr2 & !d02;
-- Node name is '~13~4~1~3~2'
-- Equation name is '~13~4~1~3~2', location is LC052, type is buried.
-- synthesized logic cell
_LC052 = LCELL( _EQ016 $ GND);
_EQ016 = addr0 & !addr1 & !addr2 & !d13
# !addr0 & !addr1 & !addr2 & !d03;
-- Node name is '~13~5~1~3~2'
-- Equation name is '~13~5~1~3~2', location is LC019, type is buried.
-- synthesized logic cell
_LC019 = LCELL( _EQ017 $ GND);
_EQ017 = addr0 & !addr1 & !addr2 & !d14
# !addr0 & !addr1 & !addr2 & !d04;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\cpld_1112\digital_0111\8_6.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,749K
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