📄 8_6.rpt
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Project Information d:\cpld_1112\digital_0111\8_6.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 01/20/2003 18:33:37
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
8_6 EPM7064SLC84-5 51 8 0 14 6 21 %
User Pins: 51 8 0
Project Information d:\cpld_1112\digital_0111\8_6.rpt
** FILE HIERARCHY **
|8_1:29|
|8_1:28|
|8_1:27|
|8_1:26|
|8_1:25|
|8_1:24|
|addr38:30|
|addr38:30|74138:4|
Device-Specific Information: d:\cpld_1112\digital_0111\8_6.rpt
8_6
***** Logic for device '8_6' compiled without errors.
Device: EPM7064SLC84-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
Device-Specific Information: d:\cpld_1112\digital_0111\8_6.rpt
8_6
** ERROR SUMMARY **
Info: Chip '8_6' in device 'EPM7064SLC84-5' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
R o o o
E u u u
V S t t t
C E d V d d
C R a C a a
d d d d G d d d I G G G G G V t d C t t d
2 3 3 3 N 3 3 3 N N N N N N E a 1 I a a 1
4 2 3 4 D 5 6 7 T D D D D D D 2 3 O 1 5 5
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
d25 | 12 74 | outdata0
VCCIO | 13 73 | d05
#TDI | 14 72 | GND
d26 | 15 71 | #TDO
d27 | 16 70 | d43
d30 | 17 69 | d47
d31 | 18 68 | d16
GND | 19 67 | d14
addr2 | 20 66 | VCCIO
addr1 | 21 65 | d07
addr0 | 22 EPM7064SLC84-5 64 | d46
#TMS | 23 63 | d03
d01 | 24 62 | #TCK
d45 | 25 61 | d06
VCCIO | 26 60 | d17
d22 | 27 59 | GND
d57 | 28 58 | d10
d56 | 29 57 | d20
d23 | 30 56 | d11
d42 | 31 55 | d21
GND | 32 54 | d02
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
d d d d d V d d d G V o o o G o d d d d V
5 5 4 5 5 C 5 4 5 N C u u u N u 0 4 1 0 C
5 4 1 3 2 C 1 0 0 D C t t t D t 0 4 2 4 C
I I d d d d I
O N a a a a O
T t t t t
a a a a
7 6 3 4
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\cpld_1112\digital_0111\8_6.rpt
8_6
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 16/16(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 1/16( 6%) 16/16(100%) 0/16( 0%) 5/36( 13%)
C: LC33 - LC48 4/16( 25%) 16/16(100%) 8/16( 50%) 25/36( 69%)
D: LC49 - LC64 9/16( 56%) 15/16( 93%) 6/16( 37%) 32/36( 88%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 63/64 ( 98%)
Total logic cells used: 14/64 ( 21%)
Total shareable expanders used: 6/64 ( 9%)
Total Turbo logic cells used: 14/64 ( 21%)
Total shareable expanders not available (n/a): 8/64 ( 12%)
Average fan-in: 7.28
Total fan-in: 102
Total input pins required: 51
Total fast input logic cells required: 0
Total output pins required: 8
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 14
Total flipflops required: 0
Total product terms required: 57
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 6
Synthesized logic cells: 6/ 64 ( 9%)
Device-Specific Information: d:\cpld_1112\digital_0111\8_6.rpt
8_6
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
22 (1) (A) INPUT 0 0 0 0 0 8 5 addr0
21 (2) (A) INPUT 0 0 0 0 0 8 6 addr1
20 (3) (A) INPUT 0 0 0 0 0 8 6 addr2
49 (37) (C) INPUT 0 0 0 0 0 0 1 d00
24 (31) (B) INPUT 0 0 0 0 0 0 1 d01
54 (41) (C) INPUT 0 0 0 0 0 0 1 d02
63 (49) (D) INPUT 0 0 0 0 0 0 1 d03
52 (40) (C) INPUT 0 0 0 0 0 0 1 d04
73 (57) (D) INPUT 0 0 0 0 0 1 0 d05
61 (47) (C) INPUT 0 0 0 0 0 1 0 d06
65 (51) (D) INPUT 0 0 0 0 0 1 0 d07
58 (45) (C) INPUT 0 0 0 0 0 0 1 d10
56 (43) (C) INPUT 0 0 0 0 0 0 1 d11
51 (39) (C) INPUT 0 0 0 0 0 0 1 d12
79 (62) (D) INPUT 0 0 0 0 0 0 1 d13
67 (52) (D) INPUT 0 0 0 0 0 0 1 d14
75 (59) (D) INPUT 0 0 0 0 0 1 0 d15
68 (53) (D) INPUT 0 0 0 0 0 1 0 d16
60 (46) (C) INPUT 0 0 0 0 0 1 0 d17
57 (44) (C) INPUT 0 0 0 0 0 1 0 d20
55 (42) (C) INPUT 0 0 0 0 0 1 0 d21
27 (29) (B) INPUT 0 0 0 0 0 1 0 d22
30 (26) (B) INPUT 0 0 0 0 0 1 0 d23
11 (10) (A) INPUT 0 0 0 0 0 1 0 d24
12 (9) (A) INPUT 0 0 0 0 0 1 0 d25
15 (7) (A) INPUT 0 0 0 0 0 1 0 d26
16 (6) (A) INPUT 0 0 0 0 0 1 0 d27
17 (5) (A) INPUT 0 0 0 0 0 1 0 d30
18 (4) (A) INPUT 0 0 0 0 0 1 0 d31
10 (11) (A) INPUT 0 0 0 0 0 1 0 d32
9 (12) (A) INPUT 0 0 0 0 0 1 0 d33
8 (13) (A) INPUT 0 0 0 0 0 1 0 d34
6 (14) (A) INPUT 0 0 0 0 0 1 0 d35
5 (15) (A) INPUT 0 0 0 0 0 1 0 d36
4 (16) (A) INPUT 0 0 0 0 0 1 0 d37
40 (18) (B) INPUT 0 0 0 0 0 1 0 d40
35 (22) (B) INPUT 0 0 0 0 0 1 0 d41
31 (25) (B) INPUT 0 0 0 0 0 1 0 d42
70 (55) (D) INPUT 0 0 0 0 0 1 0 d43
50 (38) (C) INPUT 0 0 0 0 0 1 0 d44
25 (30) (B) INPUT 0 0 0 0 0 1 0 d45
64 (50) (D) INPUT 0 0 0 0 0 1 0 d46
69 (54) (D) INPUT 0 0 0 0 0 1 0 d47
41 (17) (B) INPUT 0 0 0 0 0 1 0 d50
39 (19) (B) INPUT 0 0 0 0 0 1 0 d51
37 (20) (B) INPUT 0 0 0 0 0 1 0 d52
36 (21) (B) INPUT 0 0 0 0 0 1 0 d53
34 (23) (B) INPUT 0 0 0 0 0 1 0 d54
33 (24) (B) INPUT 0 0 0 0 0 1 0 d55
29 (27) (B) INPUT 0 0 0 0 0 1 0 d56
28 (28) (B) INPUT 0 0 0 0 0 1 0 d57
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\cpld_1112\digital_0111\8_6.rpt
8_6
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
74 58 D TRI t 1 0 1 7 1 0 0 outdata0
77 61 D TRI t 1 0 1 7 1 0 0 outdata1
80 63 D TRI t 1 0 1 7 1 0 0 outdata2
46 35 C TRI t 1 0 1 7 1 0 0 outdata3
48 36 C TRI t 1 0 1 7 1 0 0 outdata4
76 60 D TRI t 3 0 1 9 0 0 0 outdata5
45 34 C TRI t 3 0 1 9 0 0 0 outdata6
44 33 C TRI t 3 0 1 9 0 0 0 outdata7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\cpld_1112\digital_0111\8_6.rpt
8_6
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(63) 49 D SOFT s t 0 0 0 2 0 0 0 outdata7~1
(79) 62 D SOFT s t 0 0 0 5 0 1 0 ~13~1~1~3~2
(64) 50 D SOFT s t 0 0 0 5 0 1 0 ~13~2~1~3~2
(68) 53 D SOFT s t 0 0 0 5 0 1 0 ~13~3~1~3~2
(67) 52 D SOFT s t 0 0 0 5 0 1 0 ~13~4~1~3~2
(39) 19 B SOFT s t 0 0 0 5 0 1 0 ~13~5~1~3~2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\cpld_1112\digital_0111\8_6.rpt
8_6
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+- LC19 ~13~5~1~3~2
|
| Other LABs fed by signals
| that feed LAB 'B'
LC | | A B C D | Logic cells that feed LAB 'B':
Pin
22 -> * | - * * * | <-- addr0
21 -> * | - * * * | <-- addr1
20 -> * | - * * * | <-- addr2
52 -> * | - * - - | <-- d04
67 -> * | - * - - | <-- d14
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\cpld_1112\digital_0111\8_6.rpt
8_6
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------- LC35 outdata3
| +----- LC36 outdata4
| | +--- LC34 outdata6
| | | +- LC33 outdata7
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'C'
LC | | | | | A B C D | Logic cells that feed LAB 'C':
Pin
22 -> * * * * | - * * * | <-- addr0
21 -> * * * * | - * * * | <-- addr1
20 -> * * * * | - * * * | <-- addr2
61 -> - - * - | - - * - | <-- d06
65 -> - - - * | - - * - | <-- d07
68 -> - - * - | - - * - | <-- d16
60 -> - - - * | - - * - | <-- d17
30 -> * - - - | - - * - | <-- d23
11 -> - * - - | - - * - | <-- d24
15 -> - - * - | - - * - | <-- d26
16 -> - - - * | - - * - | <-- d27
9 -> * - - - | - - * - | <-- d33
8 -> - * - - | - - * - | <-- d34
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