delay.vhd

服务器的的板在载控制器的AHDL程序,包括原理图编译,用在EPM7128上(CPLD).

library ieee;
use ieee.std_logic_1164.all;
entity delay  is
port( a: in std_logic;
      b: out std_logic
    );
end entity delay;
architecture aa1 of delay is
begin
   b<=a  after 1 us;
end architecture aa1;