kvmfa.rpt

服务器的的板在载控制器的AHDL程序,包括原理图编译,用在EPM7128上(CPLD).

data4_1  = LCELL( sense2_1 $  GND);

-- Node name is ':50' = 'data4_3' 
-- Equation name is 'data4_3', location is LC060, type is buried.
data4_3  = LCELL( fail1 $  GND);

-- Node name is ':81' = 'data4_5' 
-- Equation name is 'data4_5', location is LC079, type is buried.
data4_5  = LCELL( bladein4 $  GND);

-- Node name is ':22' = 'data5_1' 
-- Equation name is 'data5_1', location is LC054, type is buried.
data5_1  = LCELL( sense2_2 $  GND);

-- Node name is ':55' = 'data5_3' 
-- Equation name is 'data5_3', location is LC065, type is buried.
data5_3  = LCELL( fail2 $  GND);

-- Node name is ':86' = 'data5_5' 
-- Equation name is 'data5_5', location is LC025, type is buried.
data5_5  = LCELL( bladein5 $  GND);

-- Node name is ':20' = 'data6_1' 
-- Equation name is 'data6_1', location is LC052, type is buried.
data6_1  = LCELL( sense2_3 $  GND);

-- Node name is ':53' = 'data6_3' 
-- Equation name is 'data6_3', location is LC080, type is buried.
data6_3  = LCELL( fail3 $  GND);

-- Node name is ':84' = 'data6_5' 
-- Equation name is 'data6_5', location is LC072, type is buried.
data6_5  = LCELL( bladein6 $  GND);

-- Node name is ':85' = 'data7_5' 
-- Equation name is 'data7_5', location is LC073, type is buried.
data7_5  = LCELL( bladein7 $  GND);

-- Node name is 'd0~fit~in1' 
-- Equation name is 'd0~fit~in1', location is LC074, type is buried.
-- synthesized logic cell 
_LC074   = LCELL( _EQ001 $  _EQ002);
  _EQ001 =  addr0 &  addr1 & !addr2 & !data0_3 &  _X001 &  _X002
         #  addr0 & !addr1 &  addr2 & !data0_5 &  _X001 &  _X002
         # !addr0 & !addr1 &  addr2 & !data0_4 &  _X001 &  _X002
         # !addr0 &  addr1 & !addr2 & !data0_2 &  _X001 &  _X002;
  _X001  = EXP(!addr0 & !addr1 & !addr2 & !data0_0);
  _X002  = EXP( addr0 & !addr1 & !addr2 & !data0_1);
  _EQ002 =  _X001 &  _X002;
  _X001  = EXP(!addr0 & !addr1 & !addr2 & !data0_0);
  _X002  = EXP( addr0 & !addr1 & !addr2 & !data0_1);

-- Node name is 'd0' 
-- Equation name is 'd0', location is LC046, type is bidir.
d0       = TRI(_LC046,  _LC011);
_LC046   = LCELL( _LC074 $  GND);

-- Node name is 'd1~fit~in1' 
-- Equation name is 'd1~fit~in1', location is LC067, type is buried.
-- synthesized logic cell 
_LC067   = LCELL( _EQ003 $  _EQ004);
  _EQ003 =  addr0 &  addr1 & !addr2 & !data1_3 &  _X003 &  _X004
         #  addr0 & !addr1 &  addr2 & !data1_5 &  _X003 &  _X004
         # !addr0 & !addr1 &  addr2 & !data1_4 &  _X003 &  _X004
         # !addr0 &  addr1 & !addr2 & !data1_2 &  _X003 &  _X004;
  _X003  = EXP(!addr0 & !addr1 & !addr2 & !data1_0);
  _X004  = EXP( addr0 & !addr1 & !addr2 & !data1_1);
  _EQ004 =  _X003 &  _X004;
  _X003  = EXP(!addr0 & !addr1 & !addr2 & !data1_0);
  _X004  = EXP( addr0 & !addr1 & !addr2 & !data1_1);

-- Node name is 'd1' 
-- Equation name is 'd1', location is LC045, type is bidir.
d1       = TRI(_LC045,  _LC011);
_LC045   = LCELL( _LC067 $  GND);

-- Node name is 'd2' 
-- Equation name is 'd2', location is LC043, type is bidir.
d2       = TRI(_LC043,  _LC011);
_LC043   = LCELL( _EQ005 $  _EQ006);
  _EQ005 =  addr0 &  addr1 & !addr2 & !data2_3 &  _X005 &  _X006
         #  addr0 & !addr1 &  addr2 & !data2_5 &  _X005 &  _X006
         # !addr0 & !addr1 &  addr2 & !data2_4 &  _X005 &  _X006
         # !addr0 &  addr1 & !addr2 & !data2_2 &  _X005 &  _X006;
  _X005  = EXP(!addr0 & !addr1 & !addr2 & !data2_0);
  _X006  = EXP( addr0 & !addr1 & !addr2 & !data2_1);
  _EQ006 =  _X005 &  _X006;
  _X005  = EXP(!addr0 & !addr1 & !addr2 & !data2_0);
  _X006  = EXP( addr0 & !addr1 & !addr2 & !data2_1);

-- Node name is 'd3' 
-- Equation name is 'd3', location is LC041, type is bidir.
d3       = TRI(_LC041,  _LC011);
_LC041   = LCELL( _EQ007 $  _EQ008);
  _EQ007 =  addr0 & !addr1 &  addr2 & !data3_5 &  _X007 &  _X008
         # !addr0 & !addr1 &  addr2 & !data3_4 &  _X007 &  _X008
         #  addr1 & !addr2 &  _X007 &  _X008;
  _X007  = EXP(!addr0 & !addr1 & !addr2 & !data3_0);
  _X008  = EXP( addr0 & !addr1 & !addr2);
  _EQ008 =  _X007 &  _X008;
  _X007  = EXP(!addr0 & !addr1 & !addr2 & !data3_0);
  _X008  = EXP( addr0 & !addr1 & !addr2);

-- Node name is 'd4~1' 
-- Equation name is 'd4~1', location is LC011, type is buried.
-- synthesized logic cell 
_LC011   = LCELL( _EQ009 $  GND);
  _EQ009 = !_LC026 &  _LC027 &  _LC029 & !_LC030 & !_LC032;

-- Node name is 'd4' 
-- Equation name is 'd4', location is LC040, type is bidir.
d4       = TRI(_LC040,  _LC011);
_LC040   = LCELL( _EQ010 $  _EQ011);
  _EQ010 =  addr0 &  addr1 & !addr2 & !data4_3 &  _X009 &  _X010
         #  addr0 & !addr1 &  addr2 & !data4_5 &  _X009 &  _X010
         # !addr0 & !addr1 &  addr2 &  _X009 &  _X010
         # !addr0 &  addr1 & !addr2 &  _X009 &  _X010;
  _X009  = EXP(!addr0 & !addr1 & !addr2);
  _X010  = EXP( addr0 & !addr1 & !addr2 & !data4_1);
  _EQ011 =  _X009 &  _X010;
  _X009  = EXP(!addr0 & !addr1 & !addr2);
  _X010  = EXP( addr0 & !addr1 & !addr2 & !data4_1);

-- Node name is 'd5' 
-- Equation name is 'd5', location is LC038, type is bidir.
d5       = TRI(_LC038,  _LC011);
_LC038   = LCELL( _EQ012 $  _EQ013);
  _EQ012 =  addr0 &  addr1 & !addr2 & !data5_3 &  _X011 &  _X012
         #  addr0 & !addr1 &  addr2 & !data5_5 &  _X011 &  _X012
         # !addr0 & !addr1 &  addr2 &  _X011 &  _X012
         # !addr0 &  addr1 & !addr2 &  _X011 &  _X012;
  _X011  = EXP(!addr0 & !addr1 & !addr2);
  _X012  = EXP( addr0 & !addr1 & !addr2 & !data5_1);
  _EQ013 =  _X011 &  _X012;
  _X011  = EXP(!addr0 & !addr1 & !addr2);
  _X012  = EXP( addr0 & !addr1 & !addr2 & !data5_1);

-- Node name is 'd6' 
-- Equation name is 'd6', location is LC037, type is bidir.
d6       = TRI(_LC037,  _LC011);
_LC037   = LCELL( _EQ014 $  _EQ015);
  _EQ014 =  addr0 &  addr1 & !addr2 & !data6_3 &  _X013 &  _X014
         #  addr0 & !addr1 &  addr2 & !data6_5 &  _X013 &  _X014
         # !addr0 & !addr1 &  addr2 &  _X013 &  _X014
         # !addr0 &  addr1 & !addr2 &  _X013 &  _X014;
  _X013  = EXP(!addr0 & !addr1 & !addr2);
  _X014  = EXP( addr0 & !addr1 & !addr2 & !data6_1);
  _EQ015 =  _X013 &  _X014;
  _X013  = EXP(!addr0 & !addr1 & !addr2);
  _X014  = EXP( addr0 & !addr1 & !addr2 & !data6_1);

-- Node name is 'd7' 
-- Equation name is 'd7', location is LC035, type is bidir.
d7       = TRI(_LC035,  _LC011);
_LC035   = LCELL( _EQ016 $  _EQ017);
  _EQ016 =  addr0 & !addr1 &  addr2 & !data7_5 &  _X015 &  _X016
         # !addr0 & !addr1 &  addr2 &  _X015 &  _X016
         #  addr1 & !addr2 &  _X015 &  _X016;
  _X015  = EXP(!addr0 & !addr1 & !addr2);
  _X016  = EXP( addr0 & !addr1 & !addr2);
  _EQ017 =  _X015 &  _X016;
  _X015  = EXP(!addr0 & !addr1 & !addr2);
  _X016  = EXP( addr0 & !addr1 & !addr2);

-- Node name is 'ram_sel' 
-- Equation name is 'ram_sel', location is LC003, type is output.
 ram_sel = LCELL( _EQ018 $  VCC);
  _EQ018 = !_LC026 & !_LC027 &  _LC029 & !_LC030;

-- Node name is ':125' 
-- Equation name is '_LC026', type is buried 
_LC026   = LCELL( sel0 $  GND);

-- Node name is ':126' 
-- Equation name is '_LC029', type is buried 
_LC029   = LCELL( sel1 $  GND);

-- Node name is ':127' 
-- Equation name is '_LC019', type is buried 
_LC019   = LCELL( wr $  GND);

-- Node name is ':128' 
-- Equation name is '_LC032', type is buried 
_LC032   = LCELL( rd $  GND);

-- Node name is ':130' 
-- Equation name is '_LC030', type is buried 
_LC030   = LCELL( reset $  GND);

-- Node name is ':178' 
-- Equation name is '_LC027', type is buried 
_LC027   = LCELL( addr15 $  GND);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                             d:\cpld_1112\digital\kvmfa.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,186K