📄 kvmfa.rpt
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24 35 C BIDIR 2 0 0 3 1 1 0 d7
46 (73) (E) INPUT 0 0 0 0 0 0 1 fail1
48 (77) (E) INPUT 0 0 0 0 0 0 1 fail2
50 (80) (E) INPUT 0 0 0 0 0 0 1 fail3
45 (72) (E) INPUT 0 0 0 0 0 0 1 ok1
47 (75) (E) INPUT 0 0 0 0 0 0 1 ok2
49 (78) (E) INPUT 0 0 0 0 0 0 1 ok3
28 (62) (D) INPUT 0 0 0 0 0 0 1 psfail0
27 (64) (D) INPUT 0 0 0 0 0 0 1 psfail1
30 (59) (D) INPUT 0 0 0 0 0 0 1 pwrgood0
29 (61) (D) INPUT 0 0 0 0 0 0 1 pwrgood1
99 (6) (A) INPUT 0 0 0 0 0 0 1 rd
89 - - INPUT 0 0 0 0 0 0 1 reset
97 (9) (A) INPUT 0 0 0 0 0 0 1 sel0
98 (8) (A) INPUT 0 0 0 0 0 0 1 sel1
63 (97) (G) INPUT 0 0 0 0 0 0 1 sense1_1
64 (99) (G) INPUT 0 0 0 0 0 0 1 sense1_2
65 (101) (G) INPUT 0 0 0 0 0 0 1 sense1_3
67 (102) (G) INPUT 0 0 0 0 0 0 1 sense2_1
68 (104) (G) INPUT 0 0 0 0 0 0 1 sense2_2
69 (105) (G) INPUT 0 0 0 0 0 0 1 sense2_3
70 (107) (G) INPUT 0 0 0 0 0 0 1 sense3_1
71 (109) (G) INPUT 0 0 0 0 0 0 1 sense3_2
72 (110) (G) INPUT 0 0 0 0 0 0 1 sense3_3
96 (11) (A) INPUT 0 0 0 0 0 0 1 sw0
94 (13) (A) INPUT 0 0 0 0 0 0 1 sw1
93 (14) (A) INPUT 0 0 0 0 0 0 1 sw2
92 (16) (A) INPUT 0 0 0 0 0 0 1 sw3
90 - - INPUT 0 0 0 0 0 0 1 wr
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\cpld_1112\digital\kvmfa.rpt
kvmfa
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
25 33 C TRI t 0 0 0 0 1 0 0 blade_rst0
54 85 F TRI t 0 0 0 0 1 0 0 blade_rst1
55 86 F TRI t 0 0 0 0 1 0 0 blade_rst2
56 88 F TRI t 0 0 0 0 1 0 0 blade_rst3
57 89 F TRI t 0 0 0 0 1 0 0 blade_rst4
58 91 F TRI t 0 0 0 0 1 0 0 blade_rst5
60 93 F TRI t 0 0 0 0 1 0 0 blade_rst6
61 94 F TRI t 0 0 0 0 1 0 0 blade_rst7
16 46 C TRI t 0 0 0 0 1 1 0 d0
17 45 C TRI t 0 0 0 0 1 1 0 d1
19 43 C TRI t 3 0 1 3 6 1 0 d2
20 41 C TRI t 2 0 0 3 3 1 0 d3
21 40 C TRI t 3 0 1 3 3 1 0 d4
22 38 C TRI t 3 0 1 3 3 1 0 d5
23 37 C TRI t 3 0 1 3 3 1 0 d6
24 35 C TRI t 2 0 0 3 1 1 0 d7
1 3 A OUTPUT t 0 0 0 0 4 0 0 ram_sel
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\cpld_1112\digital\kvmfa.rpt
kvmfa
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 74 E AND6 s t r 3 0 1 3 6 1 0 d0~fit~in1
(41) 67 E AND6 s t r 3 0 1 3 6 1 0 d1~fit~in1
(96) 11 A SOFT s t 0 0 0 0 5 0 0 d4~1
(35) 53 D LCELL t 0 0 0 1 0 0 1 data0_0 (:5)
(36) 51 D LCELL t 0 0 0 1 0 0 1 data1_0 (:6)
(37) 49 D LCELL t 0 0 0 1 0 1 0 data2_0 (:7)
- 63 D LCELL t 0 0 0 1 0 1 0 data3_0 (:8)
(28) 62 D LCELL t 0 0 0 1 0 1 0 data2_1 (:15)
(29) 61 D LCELL t 0 0 0 1 0 0 1 data1_1 (:16)
(31) 57 D LCELL t 0 0 0 1 0 0 1 data0_1 (:17)
- 50 D LCELL t 0 0 0 1 0 1 0 data4_1 (:19)
- 52 D LCELL t 0 0 0 1 0 1 0 data6_1 (:20)
(33) 54 D LCELL t 0 0 0 1 0 1 0 data5_1 (:22)
(32) 56 D LCELL t 0 0 0 1 0 1 0 data2_2 (:33)
- 58 D LCELL t 0 0 0 1 0 0 1 data1_2 (:34)
(27) 64 D LCELL t 0 0 0 1 0 0 1 data0_2 (:36)
- 55 D LCELL t 0 0 0 1 0 0 1 data0_3 (:48)
(30) 59 D LCELL t 0 0 0 1 0 1 0 data2_3 (:49)
- 60 D LCELL t 0 0 0 1 0 1 0 data4_3 (:50)
(48) 77 E LCELL t 0 0 0 1 0 0 1 data1_3 (:51)
(50) 80 E LCELL t 0 0 0 1 0 1 0 data6_3 (:53)
(40) 65 E LCELL t 0 0 0 1 0 1 0 data5_3 (:55)
(42) 69 E LCELL t 0 0 0 1 0 1 0 data3_4 (:72)
(47) 75 E LCELL t 0 0 0 1 0 0 1 data0_4 (:73)
- 76 E LCELL t 0 0 0 1 0 0 1 data1_4 (:74)
- 66 E LCELL t 0 0 0 1 0 1 0 data2_4 (:75)
- 71 E LCELL t 0 0 0 1 0 0 1 data0_5 (:79)
(49) 78 E LCELL t 0 0 0 1 0 1 0 data2_5 (:80)
- 79 E LCELL t 0 0 0 1 0 1 0 data4_5 (:81)
- 68 E LCELL t 0 0 0 1 0 0 1 data1_5 (:82)
(44) 70 E LCELL t 0 0 0 1 0 1 0 data3_5 (:83)
(45) 72 E LCELL t 0 0 0 1 0 1 0 data6_5 (:84)
(46) 73 E LCELL t 0 0 0 1 0 1 0 data7_5 (:85)
(8) 25 B LCELL t 0 0 0 1 0 1 0 data5_5 (:86)
- 26 B LCELL t 0 0 0 1 0 1 1 :125
(6) 29 B LCELL t 0 0 0 1 0 1 1 :126
(13) 19 B LCELL t 0 0 0 1 0 0 0 :127
(4) 32 B LCELL t 0 0 0 1 0 0 1 :128
(5) 30 B LCELL t 0 0 0 1 0 1 1 :130
(7) 27 B LCELL t 0 0 0 1 0 1 1 :178
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\cpld_1112\digital\kvmfa.rpt
kvmfa
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--- LC11 d4~1
| +- LC3 ram_sel
| |
| | Other LABs fed by signals
| | that feed LAB 'A'
LC | | | A B C D E F G H | Logic cells that feed LAB 'A':
Pin
89 -> - - | - * - - - - - - | <-- reset
90 -> - - | - * - - - - - - | <-- wr
LC26 -> * * | * - - - - - - - | <-- :125
LC29 -> * * | * - - - - - - - | <-- :126
LC32 -> * - | * - - - - - - - | <-- :128
LC30 -> * * | * - - - - - - - | <-- :130
LC27 -> * * | * - - - - - - - | <-- :178
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\cpld_1112\digital\kvmfa.rpt
kvmfa
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------- LC25 data5_5
| +----------- LC26 :125
| | +--------- LC29 :126
| | | +------- LC19 :127
| | | | +----- LC32 :128
| | | | | +--- LC30 :130
| | | | | | +- LC27 :178
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'B'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
Pin
6 -> - - - - - - * | - * - - - - - - | <-- addr15
79 -> * - - - - - - | - * - - - - - - | <-- bladein5
99 -> - - - - * - - | - * - - - - - - | <-- rd
89 -> - - - - - * - | - * - - - - - - | <-- reset
97 -> - * - - - - - | - * - - - - - - | <-- sel0
98 -> - - * - - - - | - * - - - - - - | <-- sel1
90 -> - - - * - - - | - * - - - - - - | <-- wr
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\cpld_1112\digital\kvmfa.rpt
kvmfa
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------- LC33 blade_rst0
| +--------------- LC46 d0
| | +------------- LC45 d1
| | | +----------- LC43 d2
| | | | +--------- LC41 d3
| | | | | +------- LC40 d4
| | | | | | +----- LC38 d5
| | | | | | | +--- LC37 d6
| | | | | | | | +- LC35 d7
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'C':
LC46 -> * - - - - - - - - | - - * - - - - - | <-- d0
Pin
14 -> - - - * * * * * * | - - * - * - - - | <-- addr0
13 -> - - - * * * * * * | - - * - * - - - | <-- addr1
12 -> - - - * * * * * * | - - * - * - - - | <-- addr2
89 -> - - - - - - - - - | - * - - - - - - | <-- reset
90 -> - - - - - - - - - | - * - - - - - - | <-- wr
LC74 -> - * - - - - - - - | - - * - - - - - | <-- d0~fit~in1
LC67 -> - - * - - - - - - | - - * - - - - - | <-- d1~fit~in1
LC49 -> - - - * - - - - - | - - * - - - - - | <-- data2_0
LC63 -> - - - - * - - - - | - - * - - - - - | <-- data3_0
LC62 -> - - - * - - - - - | - - * - - - - - | <-- data2_1
LC50 -> - - - - - * - - - | - - * - - - - - | <-- data4_1
LC52 -> - - - - - - - * - | - - * - - - - - | <-- data6_1
LC54 -> - - - - - - * - - | - - * - - - - - | <-- data5_1
LC56 -> - - - * - - - - - | - - * - - - - - | <-- data2_2
LC59 -> - - - * - - - - - | - - * - - - - - | <-- data2_3
LC60 -> - - - - - * - - - | - - * - - - - - | <-- data4_3
LC80 -> - - - - - - - * - | - - * - - - - - | <-- data6_3
LC65 -> - - - - - - * - - | - - * - - - - - | <-- data5_3
LC69 -> - - - - * - - - - | - - * - - - - - | <-- data3_4
LC66 -> - - - * - - - - - | - - * - - - - - | <-- data2_4
LC78 -> - - - * - - - - - | - - * - - - - - | <-- data2_5
LC79 -> - - - - - * - - - | - - * - - - - - | <-- data4_5
LC70 -> - - - - * - - - - | - - * - - - - - | <-- data3_5
LC72 -> - - - - - - - * - | - - * - - - - - | <-- data6_5
LC73 -> - - - - - - - - * | - - * - - - - - | <-- data7_5
LC25 -> - - - - - - * - - | - - * - - - - - | <-- data5_5
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\cpld_1112\digital\kvmfa.rpt
kvmfa
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC53 data0_0
| +----------------------------- LC51 data1_0
| | +--------------------------- LC49 data2_0
| | | +------------------------- LC63 data3_0
| | | | +----------------------- LC62 data2_1
| | | | | +--------------------- LC61 data1_1
| | | | | | +------------------- LC57 data0_1
| | | | | | | +----------------- LC50 data4_1
| | | | | | | | +--------------- LC52 data6_1
| | | | | | | | | +------------- LC54 data5_1
| | | | | | | | | | +----------- LC56 data2_2
| | | | | | | | | | | +--------- LC58 data1_2
| | | | | | | | | | | | +------- LC64 data0_2
| | | | | | | | | | | | | +----- LC55 data0_3
| | | | | | | | | | | | | | +--- LC59 data2_3
| | | | | | | | | | | | | | | +- LC60 data4_3
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'D':
Pin
46 -> - - - - - - - - - - - - - - - * | - - - * - - - - | <-- fail1
45 -> - - - - - - - - - - - - - * - - | - - - * - - - - | <-- ok1
49 -> - - - - - - - - - - - - - - * - | - - - * - - - - | <-- ok3
28 -> - - * - - - - - - - - - - - - - | - - - * - - - - | <-- psfail0
27 -> - - - * - - - - - - - - - - - - | - - - * - - - - | <-- psfail1
30 -> * - - - - - - - - - - - - - - - | - - - * - - - - | <-- pwrgood0
29 -> - * - - - - - - - - - - - - - - | - - - * - - - - | <-- pwrgood1
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