📄 kvmfa.rpt
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Project Information d:\cpld_1112\digital\kvmfa.rpt
MAX+plus II Compiler Report File
Version 9.21 2/10/99
Compiled: 11/13/2002 10:53:30
Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
kvmfa EPM7128STC100-6 42 9 8 57 16 44 %
User Pins: 42 9 8
Project Information d:\cpld_1112\digital\kvmfa.rpt
** PROJECT COMPILATION MESSAGES **
Info: Reserved unused input pin 'addr3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'addr4' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Project Information d:\cpld_1112\digital\kvmfa.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
kvmfa@14 addr0
kvmfa@13 addr1
kvmfa@12 addr2
kvmfa@10 addr3
kvmfa@9 addr4
kvmfa@6 addr15
kvmfa@85 bladein0
kvmfa@84 bladein1
kvmfa@83 bladein2
kvmfa@81 bladein3
kvmfa@80 bladein4
kvmfa@79 bladein5
kvmfa@78 bladein6
kvmfa@77 bladein7
kvmfa@25 blade_rst0
kvmfa@54 blade_rst1
kvmfa@55 blade_rst2
kvmfa@56 blade_rst3
kvmfa@57 blade_rst4
kvmfa@58 blade_rst5
kvmfa@60 blade_rst6
kvmfa@61 blade_rst7
kvmfa@16 d0
kvmfa@17 d1
kvmfa@19 d2
kvmfa@20 d3
kvmfa@21 d4
kvmfa@22 d5
kvmfa@23 d6
kvmfa@24 d7
kvmfa@46 fail1
kvmfa@48 fail2
kvmfa@50 fail3
kvmfa@45 ok1
kvmfa@47 ok2
kvmfa@49 ok3
kvmfa@28 psfail0
kvmfa@27 psfail1
kvmfa@30 pwrgood0
kvmfa@29 pwrgood1
kvmfa@1 ram_sel
kvmfa@99 rd
kvmfa@89 reset
kvmfa@97 sel0
kvmfa@98 sel1
kvmfa@63 sense1_1
kvmfa@64 sense1_2
kvmfa@65 sense1_3
kvmfa@67 sense2_1
kvmfa@68 sense2_2
kvmfa@69 sense2_3
kvmfa@70 sense3_1
kvmfa@71 sense3_2
kvmfa@72 sense3_3
kvmfa@96 sw0
kvmfa@94 sw1
kvmfa@93 sw2
kvmfa@92 sw3
kvmfa@90 wr
Project Information d:\cpld_1112\digital\kvmfa.rpt
** FILE HIERARCHY **
|8_6:175|
|8_6:175|8_1:29|
|8_6:175|8_1:28|
|8_6:175|8_1:27|
|8_6:175|8_1:26|
|8_6:175|8_1:25|
|8_6:175|8_1:24|
|8_6:175|74138:23|
|l_addr_code:177|
Device-Specific Information: d:\cpld_1112\digital\kvmfa.rpt
kvmfa
***** Logic for device 'kvmfa' compiled without errors.
Device: EPM7128STC100-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R b b b b b b b b R
E l l l l l l l l E
S V a a a a a a a a S
E C r d d d V d d d d d E
R s s C e e e e C e e e e e R
V e e s G s s s I s G G G i i i C i i i i i V
E r l l w N w w w N w e N N N n n n I n n n n n E
D d 1 0 0 D 1 2 3 T r t D D D 0 1 2 O 3 4 5 6 7 D
----------------------------------------------------_
/ 100 98 96 94 92 90 88 86 84 82 80 78 76 |_
/ 99 97 95 93 91 89 87 85 83 81 79 77 |
ram_sel | 1 75 | RESERVED
RESERVED | 2 74 | GND
VCCIO | 3 73 | #TDO
#TDI | 4 72 | sense3_3
RESERVED | 5 71 | sense3_2
addr15 | 6 70 | sense3_1
RESERVED | 7 69 | sense2_3
RESERVED | 8 68 | sense2_2
addr4 | 9 67 | sense2_1
addr3 | 10 66 | VCCIO
GND | 11 65 | sense1_3
addr2 | 12 64 | sense1_2
addr1 | 13 EPM7128STC100-6 63 | sense1_1
addr0 | 14 62 | #TCK
#TMS | 15 61 | blade_rst7
d0 | 16 60 | blade_rst6
d1 | 17 59 | GND
VCCIO | 18 58 | blade_rst5
d2 | 19 57 | blade_rst4
d3 | 20 56 | blade_rst3
d4 | 21 55 | blade_rst2
d5 | 22 54 | blade_rst1
d6 | 23 53 | RESERVED
d7 | 24 52 | RESERVED
blade_rst0 | 25 51 | VCCIO
| 27 29 31 33 35 37 39 41 43 45 47 49 _|
\ 26 28 30 32 34 36 38 40 42 44 46 48 50 |
\-----------------------------------------------------
G p p p p R R R V R R R G V R R R G R o f o f o f
N s s w w E E E C E E E N C E E E N E k a k a k a
D f f r r S S S C S S S D C S S S D S 1 i 2 i 3 i
a a g g E E E I E E E I E E E E l l l
i i o o R R R O R R R N R R R R 1 2 3
l l o o V V V V V V T V V V V
1 0 d d E E E E E E E E E E
1 0 D D D D D D D D D D
N.C. = No Connect, This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\cpld_1112\digital\kvmfa.rpt
kvmfa
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 2/16( 12%) 8/10( 80%) 0/16( 0%) 5/36( 13%)
B: LC17 - LC32 7/16( 43%) 7/10( 70%) 0/16( 0%) 7/36( 19%)
C: LC33 - LC48 9/16( 56%) 10/10(100%) 16/16(100%) 25/36( 69%)
D: LC49 - LC64 16/16(100%) 4/10( 40%) 0/16( 0%) 16/36( 44%)
E: LC65 - LC80 16/16(100%) 6/10( 60%) 6/16( 37%) 29/36( 80%)
F: LC81 - LC96 7/16( 43%) 8/10( 80%) 0/16( 0%) 7/36( 19%)
G: LC97 - LC112 0/16( 0%) 10/10(100%) 0/16( 0%) 0/36( 0%)
H: LC113 - LC128 0/16( 0%) 8/10( 80%) 0/16( 0%) 0/36( 0%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 61/80 ( 76%)
Total logic cells used: 57/128 ( 44%)
Total shareable expanders used: 16/128 ( 12%)
Total Turbo logic cells used: 57/128 ( 44%)
Total shareable expanders not available (n/a): 6/128 ( 4%)
Average fan-in: 2.22
Total fan-in: 127
Total input pins required: 42
Total fast input logic cells required: 0
Total output pins required: 9
Total bidirectional pins required: 8
Total reserved pins required 4
Total logic cells required: 57
Total flipflops required: 0
Total product terms required: 103
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 16
Synthesized logic cells: 3/ 128 ( 2%)
Device-Specific Information: d:\cpld_1112\digital\kvmfa.rpt
kvmfa
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
14 (17) (B) INPUT 0 0 0 0 0 6 2 addr0
13 (19) (B) INPUT 0 0 0 0 0 6 2 addr1
12 (21) (B) INPUT 0 0 0 0 0 6 2 addr2
10 (22) (B) INPUT 0 0 0 0 0 0 0 addr3
9 (24) (B) INPUT 0 0 0 0 0 0 0 addr4
6 (29) (B) INPUT 0 0 0 0 0 0 1 addr15
85 (128) (H) INPUT 0 0 0 0 0 0 1 bladein0
84 (126) (H) INPUT 0 0 0 0 0 0 1 bladein1
83 (125) (H) INPUT 0 0 0 0 0 0 1 bladein2
81 (123) (H) INPUT 0 0 0 0 0 0 1 bladein3
80 (121) (H) INPUT 0 0 0 0 0 0 1 bladein4
79 (120) (H) INPUT 0 0 0 0 0 0 1 bladein5
78 (118) (H) INPUT 0 0 0 0 0 0 1 bladein6
77 (117) (H) INPUT 0 0 0 0 0 0 1 bladein7
16 46 C BIDIR 0 0 0 0 1 1 0 d0
17 45 C BIDIR 0 0 0 0 1 1 0 d1
19 43 C BIDIR 3 0 1 3 6 1 0 d2
20 41 C BIDIR 2 0 0 3 3 1 0 d3
21 40 C BIDIR 3 0 1 3 3 1 0 d4
22 38 C BIDIR 3 0 1 3 3 1 0 d5
23 37 C BIDIR 3 0 1 3 3 1 0 d6
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