addrdcde.fit

服务器的的板在载控制器的AHDL程序,包括原理图编译,用在EPM7128上(CPLD).

-- MAX+plus II Compiler Fit File      
-- Version 9.21 2/10/99               
-- Compiled: 09/12/2002 18:06:40      

-- Copyright (C) 1988-1999 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "addrdcde"
BEGIN

    DEVICE = "EPM7032SLC44-5";

    "ADDR0"                        : INPUT_PIN  = 9      ; -- LC6
    "ADDR1"                        : INPUT_PIN  = 11     ; -- LC7
    "ADDR2"                        : INPUT_PIN  = 12     ; -- LC8
    "ADDR3"                        : INPUT_PIN  = 14     ; -- LC10
    "ADDR15"                       : INPUT_PIN  = 8      ; -- LC5
    "RESET_N"                      : INPUT_PIN  = 4      ; -- LC1
    "SEL0_N"                       : INPUT_PIN  = 5      ; -- LC2
    "SEL1_N"                       : INPUT_PIN  = 6      ; -- LC3
    "FPGA_SEL_N"                   : OUTPUT_PIN = 16     ; -- LC11
    "PORT0"                        : OUTPUT_PIN = 28     ; -- LC28
    "PORT1"                        : OUTPUT_PIN = 41     ; -- LC17
    "PORT2"                        : OUTPUT_PIN = 39     ; -- LC19
    "PORT3"                        : OUTPUT_PIN = 37     ; -- LC21
    "PORT4"                        : OUTPUT_PIN = 34     ; -- LC23
    "PORT5"                        : OUTPUT_PIN = 36     ; -- LC22
    "PORT6"                        : OUTPUT_PIN = 40     ; -- LC18
    "PORT7"                        : OUTPUT_PIN = 25     ; -- LC31
    "PORT8"                        : OUTPUT_PIN = 26     ; -- LC30
    "PORT9"                        : OUTPUT_PIN = 27     ; -- LC29
    "PORT10"                       : OUTPUT_PIN = 29     ; -- LC27
    "PORT11"                       : OUTPUT_PIN = 33     ; -- LC24
    "PORT12"                       : OUTPUT_PIN = 24     ; -- LC32
    "RAM_SEL_N"                    : OUTPUT_PIN = 31     ; -- LC26

END;

INTERNAL_INFO "addrdcde"
BEGIN
	DEVICE = EPM7032SLC44-5;
	LC26    : LORAX = "G39R0";
	LC32    : LORAX = "G58R0";
	LC24    : LORAX = "G33R0";
	LC27    : LORAX = "G40R0";
	LC29    : LORAX = "G55R0";
	LC30    : LORAX = "G56R0";
	LC31    : LORAX = "G57R0";
	LC18    : LORAX = "G14R0";
	LC22    : LORAX = "G31R0";
	LC23    : LORAX = "G32R0";
	LC21    : LORAX = "G30R0";
	LC19    : LORAX = "G15R0";
	LC17    : LORAX = "G13R0";
	LC28    : LORAX = "G41R0";
	LC11    : LORAX = "G36R0";
	OH4R0P8 : LORAX = "G60R0,PA29R0C0,PA29R0C1";
	OH1R0P5 : LORAX = "G44R0,PA19R0C0,PA19R0C1";
	OH2R0P6 : LORAX = "G45R0,PA22R0C0,PA22R0C1";
	OH0R0P4 : LORAX = "G43R0,PA20R0C0,PA20R0C1";
	OH9R0P14 : LORAX = "G1R0,PA4R0C1";
	OH7R0P12 : LORAX = "G63R0,PA33R0C1";
	OH6R0P11 : LORAX = "G62R0,PA31R0C1";
	OH5R0P9 : LORAX = "G61R0,PA28R0C1";
END;