addrdcde.rpt

服务器的的板在载控制器的AHDL程序,包括原理图编译,用在EPM7128上(CPLD).

* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           d:\digital\addrdcde.rpt
addrdcde

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                     Logic cells placed in LAB 'B'
        +--------------------------- LC28 PORT0
        | +------------------------- LC17 PORT1
        | | +----------------------- LC19 PORT2
        | | | +--------------------- LC21 PORT3
        | | | | +------------------- LC23 PORT4
        | | | | | +----------------- LC22 PORT5
        | | | | | | +--------------- LC18 PORT6
        | | | | | | | +------------- LC31 PORT7
        | | | | | | | | +----------- LC30 PORT8
        | | | | | | | | | +--------- LC29 PORT9
        | | | | | | | | | | +------- LC27 PORT10
        | | | | | | | | | | | +----- LC24 PORT11
        | | | | | | | | | | | | +--- LC32 PORT12
        | | | | | | | | | | | | | +- LC26 RAM_SEL_N
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':

Pin
9    -> * * * * * * * * * * * * - - | - * | <-- ADDR0
11   -> * * * * * * * * * * * * - - | - * | <-- ADDR1
12   -> * * * * * * * * * * * * * - | - * | <-- ADDR2
14   -> * * * * * * * * * * * * * - | - * | <-- ADDR3
8    -> * * * * * * * * * * * * * * | * * | <-- ADDR15
4    -> * * * * * * * * * * * * * * | * * | <-- RESET_N
5    -> * * * * * * * * * * * * * * | * * | <-- SEL0_N
6    -> * * * * * * * * * * * * * * | * * | <-- SEL1_N


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           d:\digital\addrdcde.rpt
addrdcde

** EQUATIONS **

ADDR0    : INPUT;
ADDR1    : INPUT;
ADDR2    : INPUT;
ADDR3    : INPUT;
ADDR15   : INPUT;
RESET_N  : INPUT;
SEL0_N   : INPUT;
SEL1_N   : INPUT;

-- Node name is 'FPGA_SEL_N' 
-- Equation name is 'FPGA_SEL_N', location is LC011, type is output.
 FPGA_SEL_N = LCELL( _EQ001 $  VCC);
  _EQ001 =  ADDR15 &  RESET_N & !SEL0_N &  SEL1_N;

-- Node name is 'PORT0' 
-- Equation name is 'PORT0', location is LC028, type is output.
 PORT0   = LCELL( _EQ002 $  VCC);
  _EQ002 = !ADDR0 & !ADDR1 & !ADDR2 & !ADDR3 &  ADDR15 &  RESET_N & !SEL0_N & 
              SEL1_N;

-- Node name is 'PORT1' 
-- Equation name is 'PORT1', location is LC017, type is output.
 PORT1   = LCELL( _EQ003 $  VCC);
  _EQ003 =  ADDR0 & !ADDR1 & !ADDR2 & !ADDR3 &  ADDR15 &  RESET_N & !SEL0_N & 
              SEL1_N;

-- Node name is 'PORT2' 
-- Equation name is 'PORT2', location is LC019, type is output.
 PORT2   = LCELL( _EQ004 $  VCC);
  _EQ004 = !ADDR0 &  ADDR1 & !ADDR2 & !ADDR3 &  ADDR15 &  RESET_N & !SEL0_N & 
              SEL1_N;

-- Node name is 'PORT3' 
-- Equation name is 'PORT3', location is LC021, type is output.
 PORT3   = LCELL( _EQ005 $  VCC);
  _EQ005 =  ADDR0 &  ADDR1 & !ADDR2 & !ADDR3 &  ADDR15 &  RESET_N & !SEL0_N & 
              SEL1_N;

-- Node name is 'PORT4' 
-- Equation name is 'PORT4', location is LC023, type is output.
 PORT4   = LCELL( _EQ006 $  VCC);
  _EQ006 = !ADDR0 & !ADDR1 &  ADDR2 & !ADDR3 &  ADDR15 &  RESET_N & !SEL0_N & 
              SEL1_N;

-- Node name is 'PORT5' 
-- Equation name is 'PORT5', location is LC022, type is output.
 PORT5   = LCELL( _EQ007 $  VCC);
  _EQ007 =  ADDR0 & !ADDR1 &  ADDR2 & !ADDR3 &  ADDR15 &  RESET_N & !SEL0_N & 
              SEL1_N;

-- Node name is 'PORT6' 
-- Equation name is 'PORT6', location is LC018, type is output.
 PORT6   = LCELL( _EQ008 $  VCC);
  _EQ008 = !ADDR0 &  ADDR1 &  ADDR2 & !ADDR3 &  ADDR15 &  RESET_N & !SEL0_N & 
              SEL1_N;

-- Node name is 'PORT7' 
-- Equation name is 'PORT7', location is LC031, type is output.
 PORT7   = LCELL( _EQ009 $  VCC);
  _EQ009 =  ADDR0 &  ADDR1 &  ADDR2 & !ADDR3 &  ADDR15 &  RESET_N & !SEL0_N & 
              SEL1_N;

-- Node name is 'PORT8' 
-- Equation name is 'PORT8', location is LC030, type is output.
 PORT8   = LCELL( _EQ010 $  VCC);
  _EQ010 = !ADDR0 & !ADDR1 & !ADDR2 &  ADDR3 &  ADDR15 &  RESET_N & !SEL0_N & 
              SEL1_N;

-- Node name is 'PORT9' 
-- Equation name is 'PORT9', location is LC029, type is output.
 PORT9   = LCELL( _EQ011 $  VCC);
  _EQ011 =  ADDR0 & !ADDR1 & !ADDR2 &  ADDR3 &  ADDR15 &  RESET_N & !SEL0_N & 
              SEL1_N;

-- Node name is 'PORT10' 
-- Equation name is 'PORT10', location is LC027, type is output.
 PORT10  = LCELL( _EQ012 $  VCC);
  _EQ012 = !ADDR0 &  ADDR1 & !ADDR2 &  ADDR3 &  ADDR15 &  RESET_N & !SEL0_N & 
              SEL1_N;

-- Node name is 'PORT11' 
-- Equation name is 'PORT11', location is LC024, type is output.
 PORT11  = LCELL( _EQ013 $  VCC);
  _EQ013 =  ADDR0 &  ADDR1 & !ADDR2 &  ADDR3 &  ADDR15 &  RESET_N & !SEL0_N & 
              SEL1_N;

-- Node name is 'PORT12' 
-- Equation name is 'PORT12', location is LC032, type is output.
 PORT12  = LCELL( _EQ014 $  VCC);
  _EQ014 =  ADDR2 &  ADDR3 &  ADDR15 &  RESET_N & !SEL0_N &  SEL1_N;

-- Node name is 'RAM_SEL_N' 
-- Equation name is 'RAM_SEL_N', location is LC026, type is output.
 RAM_SEL_N = LCELL( _EQ015 $  VCC);
  _EQ015 = !ADDR15 &  RESET_N & !SEL0_N &  SEL1_N;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                    d:\digital\addrdcde.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,588K