📄 addrdcde.rpt
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Project Information d:\digital\addrdcde.rpt
MAX+plus II Compiler Report File
Version 9.21 2/10/99
Compiled: 09/12/2002 18:06:40
Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
80C390 Address Decoder
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
addrdcde EPM7032SLC44-5 8 15 0 15 0 46 %
User Pins: 8 15 0
Project Information d:\digital\addrdcde.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Ignored unnecessary INPUT pin 'ADDR6'
Warning: Ignored unnecessary INPUT pin 'ADDR5'
Warning: Ignored unnecessary INPUT pin 'ADDR4'
** PROJECT TIMING MESSAGES **
Warning: Timing characteristics of device EPM7032SLC44-5 are preliminary
Device-Specific Information: d:\digital\addrdcde.rpt
addrdcde
***** Logic for device 'addrdcde' compiled without errors.
Device: EPM7032SLC44-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
R
S S E
E E S P P
L L E O O
1 0 T V G G G G G R R
_ _ _ C N N N N N T T
N N N C D D D D D 1 6
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
#TDI | 7 39 | PORT2
ADDR15 | 8 38 | #TDO
ADDR0 | 9 37 | PORT3
GND | 10 36 | PORT5
ADDR1 | 11 35 | VCC
ADDR2 | 12 EPM7032SLC44-5 34 | PORT4
#TMS | 13 33 | PORT11
ADDR3 | 14 32 | #TCK
VCC | 15 31 | RAM_SEL_N
FPGA_SEL_N | 16 30 | GND
RESERVED | 17 29 | PORT10
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V P P P P P
E E E E N C O O O O O
S S S S D C R R R R R
E E E E T T T T T
R R R R 1 7 8 9 0
V V V V 2
E E E E
D D D D
N.C. = No Connect, This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\digital\addrdcde.rpt
addrdcde
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 1/16( 6%) 11/16( 68%) 0/16( 0%) 4/36( 11%)
B: LC17 - LC32 14/16( 87%) 16/16(100%) 0/16( 0%) 8/36( 22%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 27/32 ( 84%)
Total logic cells used: 15/32 ( 46%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 15/32 ( 46%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 7.33
Total fan-in: 110
Total input pins required: 8
Total fast input logic cells required: 0
Total output pins required: 15
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 15
Total flipflops required: 0
Total product terms required: 15
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: d:\digital\addrdcde.rpt
addrdcde
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
9 (6) (A) INPUT 0 0 0 0 0 12 0 ADDR0
11 (7) (A) INPUT 0 0 0 0 0 12 0 ADDR1
12 (8) (A) INPUT 0 0 0 0 0 13 0 ADDR2
14 (10) (A) INPUT 0 0 0 0 0 13 0 ADDR3
8 (5) (A) INPUT 0 0 0 0 0 15 0 ADDR15
4 (1) (A) INPUT 0 0 0 0 0 15 0 RESET_N
5 (2) (A) INPUT 0 0 0 0 0 15 0 SEL0_N
6 (3) (A) INPUT 0 0 0 0 0 15 0 SEL1_N
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\digital\addrdcde.rpt
addrdcde
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
16 11 A OUTPUT t 0 0 0 4 0 0 0 FPGA_SEL_N
28 28 B OUTPUT t 0 0 0 8 0 0 0 PORT0
41 17 B OUTPUT t 0 0 0 8 0 0 0 PORT1
39 19 B OUTPUT t 0 0 0 8 0 0 0 PORT2
37 21 B OUTPUT t 0 0 0 8 0 0 0 PORT3
34 23 B OUTPUT t 0 0 0 8 0 0 0 PORT4
36 22 B OUTPUT t 0 0 0 8 0 0 0 PORT5
40 18 B OUTPUT t 0 0 0 8 0 0 0 PORT6
25 31 B OUTPUT t 0 0 0 8 0 0 0 PORT7
26 30 B OUTPUT t 0 0 0 8 0 0 0 PORT8
27 29 B OUTPUT t 0 0 0 8 0 0 0 PORT9
29 27 B OUTPUT t 0 0 0 8 0 0 0 PORT10
33 24 B OUTPUT t 0 0 0 8 0 0 0 PORT11
24 32 B OUTPUT t 0 0 0 6 0 0 0 PORT12
31 26 B OUTPUT t 0 0 0 4 0 0 0 RAM_SEL_N
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\digital\addrdcde.rpt
addrdcde
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+- LC11 FPGA_SEL_N
|
| Other LABs fed by signals
| that feed LAB 'A'
LC | | A B | Logic cells that feed LAB 'A':
Pin
8 -> * | * * | <-- ADDR15
4 -> * | * * | <-- RESET_N
5 -> * | * * | <-- SEL0_N
6 -> * | * * | <-- SEL1_N
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