coder.vhd

来自「服务器的的板在载控制器的AHDL程序,包括原理图编译,用在EPM7128上(CP」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
entity coder is
   port(   ina: in std_logic_vector(0 to 7);
       output: out std_logic_vector(0 to 2));
end coder;
architecture behav of coder is
 signal sint: std_logic_vector(4 downto 0);
 begin
  process(ina)
 begin
  if(ina(7)='0')then
    output<="000";
  elsif(ina(6)='0')then
   output<="100";
  elsif(ina(5)='0')then
   output<="010";
  elsif(ina(4)='0')then
   output<="110";
  elsif(ina(3)='0')then
   output<="001";
  elsif(ina(2)='0')then
   output<="101";
  elsif(ina(1)='0')then
   output<="011";
  else
   output<="111";
end if;
end process;
end behav;