📄 kvmf.rpt
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d3 = TRI(_LC041, _LC115);
_LC041 = LCELL( _EQ008 $ VCC);
_EQ008 = addr0 & !addr1 & !addr2 & !SLC2_SW1
# !addr0 & !addr1 & !addr2 & !slot3
# !addr1 & addr2
# addr1 & !addr2;
-- Node name is 'd4'
-- Equation name is 'd4', location is LC040, type is bidir.
d4 = TRI(_LC040, _LC115);
_LC040 = LCELL( _EQ009 $ VCC);
_EQ009 = addr0 & !addr1 & !addr2 & !PWR_REQ1
# !addr0 & !addr1 & !addr2 & !sw0
# !addr1 & addr2
# addr1 & !addr2;
-- Node name is 'd5'
-- Equation name is 'd5', location is LC038, type is bidir.
d5 = TRI(_LC038, _LC115);
_LC038 = LCELL( _EQ010 $ VCC);
_EQ010 = addr0 & !addr1 & !addr2 & !PWR_STA
# !addr0 & !addr1 & !addr2 & !sw1
# !addr1 & addr2
# addr1 & !addr2;
-- Node name is 'd6'
-- Equation name is 'd6', location is LC037, type is bidir.
d6 = TRI(_LC037, _LC115);
_LC037 = LCELL( _EQ011 $ VCC);
_EQ011 = addr0 & !addr1 & !addr2 & !DEDI_IO1
# !addr0 & !addr1 & !addr2 & !sw2
# !addr1 & addr2
# addr1 & !addr2;
-- Node name is 'd7~1'
-- Equation name is 'd7~1', location is LC115, type is buried.
-- synthesized logic cell
_LC115 = LCELL( _EQ012 $ GND);
_EQ012 = addr15 & !rd & reset & !sel0 & sel1;
-- Node name is 'd7'
-- Equation name is 'd7', location is LC035, type is bidir.
d7 = TRI(_LC035, _LC115);
_LC035 = LCELL( _EQ013 $ addr2);
_EQ013 = !addr0 & !addr1 & !addr2 & sw3
# !addr1 & addr2;
-- Node name is 'EN_DRV' = '|74373:296|:14'
-- Equation name is 'EN_DRV', type is output
EN_DRV = LCELL( _EQ014 $ GND);
_EQ014 = addr0 & addr1 & addr2 & addr15 & d2 & reset & !sel0 & sel1 &
!wr1
# EN_DRV & reset & _X005;
_X005 = EXP( addr0 & addr1 & addr2 & addr15 & !d2 & !sel0 & sel1 & !wr1);
-- Node name is 'fanout1'
-- Equation name is 'fanout1', location is LC005, type is output.
fanout1 = LCELL( _EQ015 $ GND);
_EQ015 = FAN0 & _LC049
# FAN2 & !_LC049;
-- Node name is 'fanout2'
-- Equation name is 'fanout2', location is LC003, type is output.
fanout2 = LCELL( _EQ016 $ GND);
_EQ016 = FAN1 & _LC049
# FAN3 & !_LC049;
-- Node name is 'heartbeat3' = '|74373:307|:17'
-- Equation name is 'heartbeat3', type is output
heartbeat3 = LCELL( _EQ017 $ GND);
_EQ017 = !addr0 & addr1 & addr2 & addr15 & d5 & reset & !sel0 & sel1 &
!wr1
# heartbeat3 & reset & _X006;
_X006 = EXP(!addr0 & addr1 & addr2 & addr15 & !d5 & !sel0 & sel1 & !wr1);
-- Node name is 'heatbeat1' = '|74373:307|:15'
-- Equation name is 'heatbeat1', type is output
heatbeat1 = LCELL( _EQ018 $ GND);
_EQ018 = !addr0 & addr1 & addr2 & addr15 & d3 & reset & !sel0 & sel1 &
!wr1
# heatbeat1 & reset & _X007;
_X007 = EXP(!addr0 & addr1 & addr2 & addr15 & !d3 & !sel0 & sel1 & !wr1);
-- Node name is 'heatbeat2' = '|74373:307|:16'
-- Equation name is 'heatbeat2', type is output
heatbeat2 = LCELL( _EQ019 $ GND);
_EQ019 = !addr0 & addr1 & addr2 & addr15 & d4 & reset & !sel0 & sel1 &
!wr1
# heatbeat2 & reset & _X008;
_X008 = EXP(!addr0 & addr1 & addr2 & addr15 & !d4 & !sel0 & sel1 & !wr1);
-- Node name is 'Mb_PWR_LED1' = '|74373:296|:15'
-- Equation name is 'Mb_PWR_LED1', type is output
Mb_PWR_LED1 = LCELL( _EQ020 $ GND);
_EQ020 = addr0 & addr1 & addr2 & addr15 & d3 & reset & !sel0 & sel1 &
!wr1
# Mb_PWR_LED1 & reset & _X009;
_X009 = EXP( addr0 & addr1 & addr2 & addr15 & !d3 & !sel0 & sel1 & !wr1);
-- Node name is 'MB_PWR_SW' = '|74373:296|:17'
-- Equation name is 'MB_PWR_SW', type is output
MB_PWR_SW = LCELL( _EQ021 $ VCC);
_EQ021 = addr0 & addr1 & addr2 & addr15 & !d5 & reset & !sel0 & sel1 &
!wr1
# !MB_PWR_SW & reset & _X010;
_X010 = EXP( addr0 & addr1 & addr2 & addr15 & d5 & !sel0 & sel1 & !wr1);
-- Node name is 'MB_RST1' = '|74373:296|:13'
-- Equation name is 'MB_RST1', type is output
MB_RST1 = LCELL( _EQ022 $ GND);
_EQ022 = addr0 & addr1 & addr2 & addr15 & d1 & reset & !sel0 & sel1 &
!wr1
# MB_RST1 & reset & _X011;
_X011 = EXP( addr0 & addr1 & addr2 & addr15 & !d1 & !sel0 & sel1 & !wr1);
-- Node name is 'muxio1' = '|74373:307|:13'
-- Equation name is 'muxio1', type is output
muxio1 = LCELL( _EQ023 $ VCC);
_EQ023 = !addr0 & addr1 & addr2 & addr15 & !d1 & reset & !sel0 & sel1 &
!wr1
# !muxio1 & reset & _X012;
_X012 = EXP(!addr0 & addr1 & addr2 & addr15 & d1 & !sel0 & sel1 & !wr1);
-- Node name is 'muxio2' = '|74373:307|:14'
-- Equation name is 'muxio2', type is output
muxio2 = LCELL( _EQ024 $ GND);
_EQ024 = !addr0 & addr1 & addr2 & addr15 & d2 & reset & !sel0 & sel1 &
!wr1
# muxio2 & reset & _X013;
_X013 = EXP(!addr0 & addr1 & addr2 & addr15 & !d2 & !sel0 & sel1 & !wr1);
-- Node name is 'PWR_EN1' = '|74373:296|:12'
-- Equation name is 'PWR_EN1', type is output
PWR_EN1 = LCELL( _EQ025 $ VCC);
_EQ025 = addr0 & addr1 & addr2 & addr15 & !d0 & reset & !sel0 & sel1 &
!wr1
# !PWR_EN1 & reset & _X014;
_X014 = EXP( addr0 & addr1 & addr2 & addr15 & d0 & !sel0 & sel1 & !wr1);
-- Node name is 'ram_sel'
-- Equation name is 'ram_sel', location is LC016, type is output.
ram_sel = LCELL( _EQ026 $ VCC);
_EQ026 = !addr15 & reset & !sel0 & sel1;
-- Node name is 'ss' = '|74373:387|:12'
-- Equation name is 'ss', type is output
ss = TRI(_LC059, _LC056);
_LC059 = LCELL( _EQ027 $ GND);
_EQ027 = !addr0 & !addr1 & addr2 & addr15 & d0 & reset & !sel0 & sel1 &
!wr1
# _LC059 & _X015;
_X015 = EXP(!addr0 & !addr1 & addr2 & addr15 & !d0 & reset & !sel0 & sel1 &
!wr1);
-- Node name is ':127' = 'wr1'
-- Equation name is 'wr1', location is LC116, type is buried.
wr1 = LCELL( wr $ GND);
-- Node name is 'zz' = '|74373:387|:13'
-- Equation name is 'zz', type is output
zz = TRI(_LC085, _LC056);
_LC085 = LCELL( _EQ028 $ GND);
_EQ028 = !addr0 & !addr1 & addr2 & addr15 & d1 & reset & !sel0 & sel1 &
!wr1
# _LC085 & _X016;
_X016 = EXP(!addr0 & !addr1 & addr2 & addr15 & !d1 & reset & !sel0 & sel1 &
!wr1);
-- Node name is '|74373:387|:14'
-- Equation name is '_LC056', type is buried
_LC056 = LCELL( _EQ029 $ GND);
_EQ029 = !addr0 & !addr1 & addr2 & addr15 & d2 & reset & !sel0 & sel1 &
!wr1
# _LC056 & _X017;
_X017 = EXP(!addr0 & !addr1 & addr2 & addr15 & !d2 & reset & !sel0 & sel1 &
!wr1);
-- Node name is '|74373:408|:14'
-- Equation name is '_LC051', type is buried
_LC051 = LCELL( _EQ030 $ GND);
_EQ030 = addr0 & !addr1 & addr2 & addr15 & d2 & reset & !sel0 & sel1 &
!wr1
# _LC051 & _X018;
_X018 = EXP( addr0 & !addr1 & addr2 & addr15 & !d2 & reset & !sel0 & sel1 &
!wr1);
-- Node name is '|74373:588|:12'
-- Equation name is '_LC049', type is buried
_LC049 = LCELL( _EQ031 $ GND);
_EQ031 = addr0 & addr1 & !addr2 & addr15 & d0 & reset & !sel0 & sel1 &
!wr1
# _LC049 & _X019;
_X019 = EXP( addr0 & addr1 & !addr2 & addr15 & !d0 & reset & !sel0 & sel1 &
!wr1);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\digital_030423\kvmf.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,159K
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