📄 kvmf.rpt
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Pin
14 -> * * * * * * * | - * * * * * * - | <-- addr0
13 -> * * * * * * * | - * * * * * * - | <-- addr1
12 -> * * * * * * * | - * * * * * * - | <-- addr2
6 -> * * * * * * * | * * - * * * * * | <-- addr15
89 -> * * * * * * * | * * - * * * * * | <-- reset
97 -> * * * * * * * | * * - * * * * * | <-- sel0
98 -> * * * * * * * | * * - * * * * * | <-- sel1
90 -> - - - - - - - | - - - - - - - * | <-- wr
LC46 -> * * - * - - * | - - - * - * - - | <-- d0
LC43 -> - - - - * * - | - - - * - * * - | <-- d2
LC38 -> - - * - - - - | - - - * - * - - | <-- d5
LC116-> * * * * * * * | - * - * * * * - | <-- wr1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\digital_030423\kvmf.rpt
kvmf
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+----- LC70 DED_LED1
| +--- LC77 heatbeat1
| | +- LC80 heatbeat2
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'E'
LC | | | | A B C D E F G H | Logic cells that feed LAB 'E':
LC70 -> * - - | - - - - * - - - | <-- DED_LED1
LC77 -> - * - | - - - - * - - - | <-- heatbeat1
LC80 -> - - * | - - - - * - - - | <-- heatbeat2
Pin
14 -> * * * | - * * * * * * - | <-- addr0
13 -> * * * | - * * * * * * - | <-- addr1
12 -> * * * | - * * * * * * - | <-- addr2
6 -> * * * | * * - * * * * * | <-- addr15
89 -> * * * | * * - * * * * * | <-- reset
97 -> * * * | * * - * * * * * | <-- sel0
98 -> * * * | * * - * * * * * | <-- sel1
90 -> - - - | - - - - - - - * | <-- wr
LC41 -> - * - | - * - - * - - - | <-- d3
LC40 -> * - * | - - - - * - - - | <-- d4
LC116-> * * * | - * - * * * * - | <-- wr1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\digital_030423\kvmf.rpt
kvmf
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+------------- LC94 bb
| +----------- LC86 MB_PWR_SW
| | +--------- LC91 MB_RST1
| | | +------- LC81 muxio1
| | | | +----- LC93 muxio2
| | | | | +--- LC89 PWR_EN1
| | | | | | +- LC85 zz
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'F'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
LC94 -> * - - - - - - | - - - - - * - - | <-- bb
LC86 -> - * - - - - - | - - - - - * - - | <-- MB_PWR_SW
LC91 -> - - * - - - - | - - - - - * - - | <-- MB_RST1
LC81 -> - - - * - - - | - - - - - * - - | <-- muxio1
LC93 -> - - - - * - - | - - - - - * - - | <-- muxio2
LC89 -> - - - - - * - | - - - - - * - - | <-- PWR_EN1
LC85 -> - - - - - - * | - - - - - * - - | <-- zz
Pin
14 -> * * * * * * * | - * * * * * * - | <-- addr0
13 -> * * * * * * * | - * * * * * * - | <-- addr1
12 -> * * * * * * * | - * * * * * * - | <-- addr2
6 -> * * * * * * * | * * - * * * * * | <-- addr15
89 -> * * * * * * * | * * - * * * * * | <-- reset
97 -> * * * * * * * | * * - * * * * * | <-- sel0
98 -> * * * * * * * | * * - * * * * * | <-- sel1
90 -> - - - - - - - | - - - - - - - * | <-- wr
LC46 -> - - - - - * - | - - - * - * - - | <-- d0
LC45 -> * - * * - - * | - - - - - * - - | <-- d1
LC43 -> - - - - * - - | - - - * - * * - | <-- d2
LC38 -> - * - - - - - | - - - * - * - - | <-- d5
LC116-> * * * * * * * | - * - * * * * - | <-- wr1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\digital_030423\kvmf.rpt
kvmf
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+- LC97 EN_DRV
|
| Other LABs fed by signals
| that feed LAB 'G'
LC | | A B C D E F G H | Logic cells that feed LAB 'G':
LC97 -> * | - - - - - - * - | <-- EN_DRV
Pin
14 -> * | - * * * * * * - | <-- addr0
13 -> * | - * * * * * * - | <-- addr1
12 -> * | - * * * * * * - | <-- addr2
6 -> * | * * - * * * * * | <-- addr15
89 -> * | * * - * * * * * | <-- reset
97 -> * | * * - * * * * * | <-- sel0
98 -> * | * * - * * * * * | <-- sel1
90 -> - | - - - - - - - * | <-- wr
LC43 -> * | - - - * - * * - | <-- d2
LC116-> * | - * - * * * * - | <-- wr1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\digital_030423\kvmf.rpt
kvmf
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+----------- LC115 d7~1
| +--------- LC116 wr1
| | +------- LC114 data0_5
| | | +----- LC113 data1_5
| | | | +--- LC128 data1_4
| | | | | +- LC120 data0_4
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'H'
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
Pin
6 -> * - - - - - | * * - * * * * * | <-- addr15
53 -> - - - - * - | - - - - - - - * | <-- keyboadclk
56 -> - - - - - * | - - - - - - - * | <-- keyboarddata
47 -> - - - * - - | - - - - - - - * | <-- mouseclk
45 -> - - * - - - | - - - - - - - * | <-- mousedata
99 -> * - - - - - | - - - - - - - * | <-- rd
89 -> * - - - - - | * * - * * * * * | <-- reset
97 -> * - - - - - | * * - * * * * * | <-- sel0
98 -> * - - - - - | * * - * * * * * | <-- sel1
90 -> - * - - - - | - - - - - - - * | <-- wr
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\digital_030423\kvmf.rpt
kvmf
** EQUATIONS **
addr0 : INPUT;
addr1 : INPUT;
addr2 : INPUT;
addr3 : INPUT;
addr4 : INPUT;
addr5 : INPUT;
addr6 : INPUT;
addr15 : INPUT;
DEDI_IO1 : INPUT;
FAN0 : INPUT;
FAN1 : INPUT;
FAN2 : INPUT;
FAN3 : INPUT;
keyboadclk : INPUT;
keyboarddata : INPUT;
mouseclk : INPUT;
mousedata : INPUT;
PWR_REQ1 : INPUT;
PWR_STA : INPUT;
PWR_SW1 : INPUT;
rd : INPUT;
reset : INPUT;
RST_SW1 : INPUT;
sel0 : INPUT;
sel1 : INPUT;
SLC1_SW1 : INPUT;
SLC2_SW1 : INPUT;
slot0 : INPUT;
slot1 : INPUT;
slot2 : INPUT;
slot3 : INPUT;
sw0 : INPUT;
sw1 : INPUT;
sw2 : INPUT;
sw3 : INPUT;
wr : INPUT;
-- Node name is 'aa' = '|74373:408|:12'
-- Equation name is 'aa', type is output
aa = TRI(_LC064, _LC051);
_LC064 = LCELL( _EQ001 $ GND);
_EQ001 = addr0 & !addr1 & addr2 & addr15 & d0 & reset & !sel0 & sel1 &
!wr1
# _LC064 & _X001;
_X001 = EXP( addr0 & !addr1 & addr2 & addr15 & !d0 & reset & !sel0 & sel1 &
!wr1);
-- Node name is 'backdediled' = '|74373:307|:12'
-- Equation name is 'backdediled', type is output
backdediled = LCELL( _EQ002 $ VCC);
_EQ002 = !addr0 & addr1 & addr2 & addr15 & !d0 & reset & !sel0 & sel1 &
!wr1
# !backdediled & reset & _X002;
_X002 = EXP(!addr0 & addr1 & addr2 & addr15 & d0 & !sel0 & sel1 & !wr1);
-- Node name is 'bb' = '|74373:408|:13'
-- Equation name is 'bb', type is output
bb = TRI(_LC094, _LC051);
_LC094 = LCELL( _EQ003 $ GND);
_EQ003 = addr0 & !addr1 & addr2 & addr15 & d1 & reset & !sel0 & sel1 &
!wr1
# _LC094 & _X003;
_X003 = EXP( addr0 & !addr1 & addr2 & addr15 & !d1 & reset & !sel0 & sel1 &
!wr1);
-- Node name is ':556' = 'data0_4'
-- Equation name is 'data0_4', location is LC120, type is buried.
data0_4 = LCELL( keyboarddata $ GND);
-- Node name is ':276' = 'data0_5'
-- Equation name is 'data0_5', location is LC114, type is buried.
data0_5 = LCELL( mousedata $ GND);
-- Node name is ':555' = 'data1_4'
-- Equation name is 'data1_4', location is LC128, type is buried.
data1_4 = LCELL( keyboadclk $ GND);
-- Node name is ':279' = 'data1_5'
-- Equation name is 'data1_5', location is LC113, type is buried.
data1_5 = LCELL( mouseclk $ GND);
-- Node name is 'DED_LED1' = '|74373:296|:16'
-- Equation name is 'DED_LED1', type is output
DED_LED1 = LCELL( _EQ004 $ GND);
_EQ004 = addr0 & addr1 & addr2 & addr15 & d4 & reset & !sel0 & sel1 &
!wr1
# DED_LED1 & reset & _X004;
_X004 = EXP( addr0 & addr1 & addr2 & addr15 & !d4 & !sel0 & sel1 & !wr1);
-- Node name is 'd0'
-- Equation name is 'd0', location is LC046, type is bidir.
d0 = TRI(_LC046, _LC115);
_LC046 = LCELL( _EQ005 $ VCC);
_EQ005 = addr0 & !addr1 & addr2 & !data0_5
# !addr0 & !addr1 & addr2 & !data0_4
# addr0 & !addr1 & !addr2 & !PWR_SW1
# !addr0 & !addr1 & !addr2 & !slot0
# addr1 & !addr2;
-- Node name is 'd1'
-- Equation name is 'd1', location is LC045, type is bidir.
d1 = TRI(_LC045, _LC115);
_LC045 = LCELL( _EQ006 $ VCC);
_EQ006 = addr0 & !addr1 & addr2 & !data1_5
# !addr0 & !addr1 & addr2 & !data1_4
# addr0 & !addr1 & !addr2 & !RST_SW1
# !addr0 & !addr1 & !addr2 & !slot1
# addr1 & !addr2;
-- Node name is 'd2'
-- Equation name is 'd2', location is LC043, type is bidir.
d2 = TRI(_LC043, _LC115);
_LC043 = LCELL( _EQ007 $ VCC);
_EQ007 = addr0 & !addr1 & !addr2 & !SLC1_SW1
# !addr0 & !addr1 & !addr2 & !slot2
# !addr1 & addr2
# addr1 & !addr2;
-- Node name is 'd3'
-- Equation name is 'd3', location is LC041, type is bidir.
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