📄 kvmf.rpt
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Total fast input logic cells required: 0
Total output pins required: 19
Total bidirectional pins required: 8
Total reserved pins required 4
Total logic cells required: 36
Total flipflops required: 0
Total product terms required: 101
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 19
Synthesized logic cells: 1/ 128 ( 0%)
Device-Specific Information: d:\digital_030423\kvmf.rpt
kvmf
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
14 (17) (B) INPUT 0 0 0 0 0 24 3 addr0
13 (19) (B) INPUT 0 0 0 0 0 24 3 addr1
12 (21) (B) INPUT 0 0 0 0 0 24 3 addr2
10 (22) (B) INPUT 0 0 0 0 0 0 0 addr3
9 (24) (B) INPUT 0 0 0 0 0 0 0 addr4
8 (25) (B) INPUT 0 0 0 0 0 0 0 addr5
7 (27) (B) INPUT 0 0 0 0 0 0 0 addr6
6 (29) (B) INPUT 0 0 0 0 0 17 4 addr15
28 (62) (D) INPUT 0 0 0 0 0 1 0 DEDI_IO1
16 46 C BIDIR 1 0 1 5 2 4 1 d0
17 45 C BIDIR 1 0 1 5 2 4 0 d1
19 43 C BIDIR 0 0 0 5 0 2 2 d2
20 41 C BIDIR 0 0 0 5 0 2 0 d3
21 40 C BIDIR 0 0 0 5 0 2 0 d4
22 38 C BIDIR 0 0 0 5 0 2 0 d5
23 37 C BIDIR 0 0 0 5 0 0 0 d6
24 35 C BIDIR 0 0 0 4 0 0 0 d7
33 (54) (D) INPUT 0 0 0 0 0 1 0 FAN0
94 (13) (A) INPUT 0 0 0 0 0 1 0 FAN1
76 (115) (H) INPUT 0 0 0 0 0 1 0 FAN2
41 (67) (E) INPUT 0 0 0 0 0 1 0 FAN3
53 (83) (F) INPUT 0 0 0 0 0 0 1 keyboadclk
56 (88) (F) INPUT 0 0 0 0 0 0 1 keyboarddata
47 (75) (E) INPUT 0 0 0 0 0 0 1 mouseclk
45 (72) (E) INPUT 0 0 0 0 0 0 1 mousedata
25 (33) (C) INPUT 0 0 0 0 0 1 0 PWR_REQ1
36 (51) (D) INPUT 0 0 0 0 0 1 0 PWR_STA
31 (57) (D) INPUT 0 0 0 0 0 1 0 PWR_SW1
99 (6) (A) INPUT 0 0 0 0 0 0 1 rd
89 - - INPUT 0 0 0 0 0 17 4 reset
49 (78) (E) INPUT 0 0 0 0 0 1 0 RST_SW1
97 (9) (A) INPUT 0 0 0 0 0 17 4 sel0
98 (8) (A) INPUT 0 0 0 0 0 17 4 sel1
37 (49) (D) INPUT 0 0 0 0 0 1 0 SLC1_SW1
32 (56) (D) INPUT 0 0 0 0 0 1 0 SLC2_SW1
64 (99) (G) INPUT 0 0 0 0 0 1 0 slot0
65 (101) (G) INPUT 0 0 0 0 0 1 0 slot1
67 (102) (G) INPUT 0 0 0 0 0 1 0 slot2
68 (104) (G) INPUT 0 0 0 0 0 1 0 slot3
69 (105) (G) INPUT 0 0 0 0 0 1 0 sw0
70 (107) (G) INPUT 0 0 0 0 0 1 0 sw1
71 (109) (G) INPUT 0 0 0 0 0 1 0 sw2
72 (110) (G) INPUT 0 0 0 0 0 1 0 sw3
90 - - INPUT 0 0 0 0 0 0 1 wr
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\digital_030423\kvmf.rpt
kvmf
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
27 64 D TRI t 1 0 0 7 3 1 0 aa
35 53 D OUTPUT t 1 0 0 7 3 1 0 backdediled
61 94 F TRI t 1 0 0 7 3 1 0 bb
44 70 E OUTPUT t 1 0 0 7 3 1 0 DED_LED1
16 46 C TRI t 1 0 1 5 2 4 1 d0
17 45 C TRI t 1 0 1 5 2 4 0 d1
19 43 C TRI t 0 0 0 5 0 2 2 d2
20 41 C TRI t 0 0 0 5 0 2 0 d3
21 40 C TRI t 0 0 0 5 0 2 0 d4
22 38 C TRI t 0 0 0 5 0 2 0 d5
23 37 C TRI t 0 0 0 5 0 0 0 d6
24 35 C TRI t 0 0 0 4 0 0 0 d7
63 97 G OUTPUT t 1 0 0 7 3 1 0 EN_DRV
100 5 A OUTPUT t 0 0 0 2 1 0 0 fanout1
1 3 A OUTPUT t 0 0 0 2 1 0 0 fanout2
29 61 D OUTPUT t 1 0 0 7 3 1 0 heartbeat3
48 77 E OUTPUT t 1 0 0 7 3 1 0 heatbeat1
50 80 E OUTPUT t 1 0 0 7 3 1 0 heatbeat2
5 30 B OUTPUT t 1 0 0 7 3 1 0 Mb_PWR_LED1
55 86 F OUTPUT t 1 0 0 7 3 1 0 MB_PWR_SW
58 91 F OUTPUT t 1 0 0 7 3 1 0 MB_RST1
52 81 F OUTPUT t 1 0 0 7 3 1 0 muxio1
60 93 F OUTPUT t 1 0 0 7 3 1 0 muxio2
57 89 F OUTPUT t 1 0 0 7 3 1 0 PWR_EN1
92 16 A OUTPUT t 0 0 0 4 0 0 0 ram_sel
30 59 D TRI t 1 0 0 7 3 1 0 ss
54 85 F TRI t 1 0 0 7 3 1 0 zz
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\digital_030423\kvmf.rpt
kvmf
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(76) 115 H SOFT s t 0 0 0 5 0 0 0 d7~1
- 116 H LCELL t 0 0 0 1 0 16 3 wr1 (:127)
- 114 H LCELL t 0 0 0 1 0 1 0 data0_5 (:276)
(75) 113 H LCELL t 0 0 0 1 0 1 0 data1_5 (:279)
(85) 128 H LCELL t 0 0 0 1 0 1 0 data1_4 (:555)
(79) 120 H LCELL t 0 0 0 1 0 1 0 data0_4 (:556)
(32) 56 D LCELL t 1 0 0 7 3 0 1 |74373:387|:14
(36) 51 D LCELL t 1 0 0 7 3 0 1 |74373:408|:14
(37) 49 D LCELL t 1 0 0 7 3 2 1 |74373:588|:12
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\digital_030423\kvmf.rpt
kvmf
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----- LC5 fanout1
| +--- LC3 fanout2
| | +- LC16 ram_sel
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'A'
LC | | | | A B C D E F G H | Logic cells that feed LAB 'A':
Pin
6 -> - - * | * * - * * * * * | <-- addr15
33 -> * - - | * - - - - - - - | <-- FAN0
94 -> - * - | * - - - - - - - | <-- FAN1
76 -> * - - | * - - - - - - - | <-- FAN2
41 -> - * - | * - - - - - - - | <-- FAN3
89 -> - - * | * * - * * * * * | <-- reset
97 -> - - * | * * - * * * * * | <-- sel0
98 -> - - * | * * - * * * * * | <-- sel1
90 -> - - - | - - - - - - - * | <-- wr
LC49 -> * * - | * - - * - - - - | <-- |74373:588|:12
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\digital_030423\kvmf.rpt
kvmf
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+- LC30 Mb_PWR_LED1
|
| Other LABs fed by signals
| that feed LAB 'B'
LC | | A B C D E F G H | Logic cells that feed LAB 'B':
LC30 -> * | - * - - - - - - | <-- Mb_PWR_LED1
Pin
14 -> * | - * * * * * * - | <-- addr0
13 -> * | - * * * * * * - | <-- addr1
12 -> * | - * * * * * * - | <-- addr2
6 -> * | * * - * * * * * | <-- addr15
89 -> * | * * - * * * * * | <-- reset
97 -> * | * * - * * * * * | <-- sel0
98 -> * | * * - * * * * * | <-- sel1
90 -> - | - - - - - - - * | <-- wr
LC41 -> * | - * - - * - - - | <-- d3
LC116-> * | - * - * * * * - | <-- wr1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\digital_030423\kvmf.rpt
kvmf
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------------- LC46 d0
| +------------- LC45 d1
| | +----------- LC43 d2
| | | +--------- LC41 d3
| | | | +------- LC40 d4
| | | | | +----- LC38 d5
| | | | | | +--- LC37 d6
| | | | | | | +- LC35 d7
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'C'
LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'C':
Pin
14 -> * * * * * * * * | - * * * * * * - | <-- addr0
13 -> * * * * * * * * | - * * * * * * - | <-- addr1
12 -> * * * * * * * * | - * * * * * * - | <-- addr2
28 -> - - - - - - * - | - - * - - - - - | <-- DEDI_IO1
25 -> - - - - * - - - | - - * - - - - - | <-- PWR_REQ1
36 -> - - - - - * - - | - - * - - - - - | <-- PWR_STA
31 -> * - - - - - - - | - - * - - - - - | <-- PWR_SW1
89 -> - - - - - - - - | * * - * * * * * | <-- reset
49 -> - * - - - - - - | - - * - - - - - | <-- RST_SW1
37 -> - - * - - - - - | - - * - - - - - | <-- SLC1_SW1
32 -> - - - * - - - - | - - * - - - - - | <-- SLC2_SW1
64 -> * - - - - - - - | - - * - - - - - | <-- slot0
65 -> - * - - - - - - | - - * - - - - - | <-- slot1
67 -> - - * - - - - - | - - * - - - - - | <-- slot2
68 -> - - - * - - - - | - - * - - - - - | <-- slot3
69 -> - - - - * - - - | - - * - - - - - | <-- sw0
70 -> - - - - - * - - | - - * - - - - - | <-- sw1
71 -> - - - - - - * - | - - * - - - - - | <-- sw2
72 -> - - - - - - - * | - - * - - - - - | <-- sw3
90 -> - - - - - - - - | - - - - - - - * | <-- wr
LC114-> * - - - - - - - | - - * - - - - - | <-- data0_5
LC113-> - * - - - - - - | - - * - - - - - | <-- data1_5
LC128-> - * - - - - - - | - - * - - - - - | <-- data1_4
LC120-> * - - - - - - - | - - * - - - - - | <-- data0_4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\digital_030423\kvmf.rpt
kvmf
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------- LC64 aa
| +----------- LC53 backdediled
| | +--------- LC61 heartbeat3
| | | +------- LC59 ss
| | | | +----- LC56 |74373:387|:14
| | | | | +--- LC51 |74373:408|:14
| | | | | | +- LC49 |74373:588|:12
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'D'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'D':
LC64 -> * - - - - - - | - - - * - - - - | <-- aa
LC53 -> - * - - - - - | - - - * - - - - | <-- backdediled
LC61 -> - - * - - - - | - - - * - - - - | <-- heartbeat3
LC59 -> - - - * - - - | - - - * - - - - | <-- ss
LC56 -> - - - - * - - | - - - * - - - - | <-- |74373:387|:14
LC51 -> - - - - - * - | - - - * - - - - | <-- |74373:408|:14
LC49 -> - - - - - - * | * - - * - - - - | <-- |74373:588|:12
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