block1.vhd

来自「服务器的的板在载控制器的AHDL程序,包括原理图编译,用在EPM7128上(CP」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity block1 is
  port(   clk:in std_logic;
           q:buffer std_logic_vector(4 downto 0)
       );
end block1;
architecture one of block1 is
begin
  process(clk)
  begin
     if clk'event and clk='1' then
        if q=13 then 
           q<="00000";
        else
           q<=q+1;
        end if;
      end if;
  end process;
end architecture one;