60计数counter60.vhd.txt

来自「具有多种功能的电子钟：闹钟」· 文本 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter60 is
port(cp :in std_logic;
        bin :out std_logic_vector(5 downto 0);
        s :in std_logic;
        clr :in std_logic;
        ec :in std_logic;
        cy60 :out std_logic);
end counter60;
architecture a of counter60 is
     signal q : std_logic_vector(5 downto 0);
     signal rst,dly : std_logic;
begin
    process(cp,rst)
     begin
          if rst='1' then
               q<="000000";
          else if cp'event and cp ='1' then
              dly<=q(5);
              if ec='1' then
                    q<=q+1;
              end if;
               end if;
          end if;
      end process;
      cy60<=not q(5) and dly;
      rst<='1'when q=60 or clr='1' else
           '0';
      bin<= q when s='1' else
           "000000";
end a;