tcdg.vhdl.txt

des vhld 源码 程序完成了DES的编码和解码功能

--

-- ****************************************************************************
--                                                                           --
--     Copyright @ 1999                                                      --
--                                                                           --
--     Tetraedre SARL,  chenes 19,   2072 Saint-Blaise,  Switzerland         --
--                                                                           --
-- ****************************************************************************
--                                                                           --
-- Filename  : tcdg.vhd                                                      --
--                                                                           --
-- ****************************************************************************
--                                                                           --
-- WARNING: This file is the property of Tetraedre SARL, Switzerland. This   --
-- file is protected by a copyright. The reading, copying, compilation,      --
-- synthesis and other use of this file is forbidden without a written       --
-- agreement signed by Tetraedre SARL, Switzerland.                          --
--                                                                           --
-- IN NO EVENT SHALL TETRAEDRE SARL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER--
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING   --
-- FROM, OUT OF OR IN CONNECTION WITH THIS DESCRIPTION OR THE USE OF IT.     --
--                                                                           --
-- ****************************************************************************





----------------------------------------------------------------------------
------------------------------------------------------------------ SUBKEY --
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity subkey is
    port (
        key    : in  std_logic_vector(63 downto 0);
        sel    : in  std_logic_vector(3 downto 0);
        subkey : out std_logic_vector(47 downto 0)
    );
end;


---------- Architecture subkey ---------- 
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of subkey is
    signal kkey_1  : std_logic_vector(47 downto 0);
    signal kkey_2  : std_logic_vector(47 downto 0);
    signal kkey_3  : std_logic_vector(47 downto 0);
    signal kkey_4  : std_logic_vector(47 downto 0);
    signal kkey_5  : std_logic_vector(47 downto 0);
    signal kkey_6  : std_logic_vector(47 downto 0);
    signal kkey_7  : std_logic_vector(47 downto 0);
    signal kkey_8  : std_logic_vector(47 downto 0);
    signal kkey_9  : std_logic_vector(47 downto 0);
    signal kkey_10 : std_logic_vector(47 downto 0);
    signal kkey_11 : std_logic_vector(47 downto 0);
    signal kkey_12 : std_logic_vector(47 downto 0);
    signal kkey_13 : std_logic_vector(47 downto 0);
    signal kkey_14 : std_logic_vector(47 downto 0);
    signal kkey_15 : std_logic_vector(47 downto 0);
    signal kkey_16 : std_logic_vector(47 downto 0);
    signal q       : std_logic_vector(63 downto 0);
    signal s0_0    : std_logic_vector(47 downto 0);
    signal s0_1    : std_logic_vector(47 downto 0);
    signal s0_2    : std_logic_vector(47 downto 0);
    signal s0_3    : std_logic_vector(47 downto 0);
    signal s0_4    : std_logic_vector(47 downto 0);
    signal s0_5    : std_logic_vector(47 downto 0);
    signal s0_6    : std_logic_vector(47 downto 0);
    signal s0_7    : std_logic_vector(47 downto 0);
    signal s1_0    : std_logic_vector(47 downto 0);
    signal s1_1    : std_logic_vector(47 downto 0);
    signal s1_2    : std_logic_vector(47 downto 0);
    signal s1_3    : std_logic_vector(47 downto 0);
    signal s2_0    : std_logic_vector(47 downto 0);
    signal s2_1    : std_logic_vector(47 downto 0);

begin

    q <= key;


    P1 : process(q)
    begin
        kkey_1<=q(54)&q(13)&q(30)&q(4)&q(15)&q(47)&q(31)&q(7)&q(62)&q(55)&q(45)&q(22)&q(61)&q(29)&q(38)&q(39)&q(20)&q(6)&q(5)&q(63)&q(28)&q(37)&q(46)&q(23)&q(42)&q(36)&q(25)&q(10)&q(27)&q(60)&q(17)&q(34)&q(59)&q(11)&q(41)&q(35)&q(3)&q(43)&q(26)&q(1)&q(49)&q(44)&q(19)&q(50)&q(51)&q(2)&q(9)&q(33);
        kkey_2<=q(62)&q(21)&q(38)&q(12)&q(23)&q(55)&q(39)&q(15)&q(5)&q(63)&q(53)&q(30)&q(4)&q(37)&q(46)&q(47)&q(28)&q(14)&q(13)&q(6)&q(7)&q(45)&q(54)&q(31)&q(50)&q(44)&q(33)&q(18)&q(35)&q(1)&q(25)&q(42)&q(36)&q(19)&q(49)&q(43)&q(11)&q(51)&q(34)&q(9)&q(57)&q(52)&q(27)&q(58)&q(59)&q(10)&q(17)&q(41);
        kkey_3<=q(13)&q(37)&q(54)&q(28)&q(39)&q(6)&q(55)&q(31)&q(21)&q(14)&q(4)&q(46)&q(20)&q(53)&q(62)&q(63)&q(15)&q(30)&q(29)&q(22)&q(23)&q(61)&q(5)&q(47)&q(3)&q(60)&q(49)&q(34)&q(51)&q(17)&q(41)&q(58)&q(52)&q(35)&q(2)&q(59)&q(27)&q(36)&q(50)&q(25)&q(10)&q(1)&q(43)&q(11)&q(44)&q(26)&q(33)&q(57);
        kkey_4<=q(29)&q(53)&q(5)&q(15)&q(55)&q(22)&q(6)&q(47)&q(37)&q(30)&q(20)&q(62)&q(7)&q(4)&q(13)&q(14)&q(31)&q(46)&q(45)&q(38)&q(39)&q(12)&q(21)&q(63)&q(19)&q(9)&q(2)&q(50)&q(36)&q(33)&q(57)&q(11)&q(1)&q(51)&q(18)&q(44)&q(43)&q(52)&q(3)&q(41)&q(26)&q(17)&q(59)&q(27)&q(60)&q(42)&q(49)&q(10);
        kkey_5<=q(45)&q(4)&q(21)&q(31)&q(6)&q(38)&q(22)&q(63)&q(53)&q(46)&q(7)&q(13)&q(23)&q(20)&q(29)&q(30)&q(47)&q(62)&q(61)&q(54)&q(55)&q(28)&q(37)&q(14)&q(35)&q(25)&q(18)&q(3)&q(52)&q(49)&q(10)&q(27)&q(17)&q(36)&q(34)&q(60)&q(59)&q(1)&q(19)&q(57)&q(42)&q(33)&q(44)&q(43)&q(9)&q(58)&q(2)&q(26);
        kkey_6<=q(61)&q(20)&q(37)&q(47)&q(22)&q(54)&q(38)&q(14)&q(4)&q(62)&q(23)&q(29)&q(39)&q(7)&q(45)&q(46)&q(63)&q(13)&q(12)&q(5)&q(6)&q(15)&q(53)&q(30)&q(51)&q(41)&q(34)&q(19)&q(1)&q(2)&q(26)&q(43)&q(33)&q(52)&q(50)&q(9)&q(44)&q(17)&q(35)&q(10)&q(58)&q(49)&q(60)&q(59)&q(25)&q(11)&q(18)&q(42);
        kkey_7<=q(12)&q(7)&q(53)&q(63)&q(38)&q(5)&q(54)&q(30)&q(20)&q(13)&q(39)&q(45)&q(55)&q(23)&q(61)&q(62)&q(14)&q(29)&q(28)&q(21)&q(22)&q(31)&q(4)&q(46)&q(36)&q(57)&q(50)&q(35)&q(17)&q(18)&q(42)&q(59)&q(49)&q(1)&q(3)&q(25)&q(60)&q(33)&q(51)&q(26)&q(11)&q(2)&q(9)&q(44)&q(41)&q(27)&q(34)&q(58);
        kkey_8<=q(28)&q(23)&q(4)&q(14)&q(54)&q(21)&q(5)&q(46)&q(7)&q(29)&q(55)&q(61)&q(6)&q(39)&q(12)&q(13)&q(30)&q(45)&q(15)&q(37)&q(38)&q(47)&q(20)&q(62)&q(52)&q(10)&q(3)&q(51)&q(33)&q(34)&q(58)&q(44)&q(2)&q(17)&q(19)&q(41)&q(9)&q(49)&q(36)&q(42)&q(27)&q(18)&q(25)&q(60)&q(57)&q(43)&q(50)&q(11);
        kkey_9<=q(7)&q(31)&q(12)&q(22)&q(62)&q(29)&q(13)&q(54)&q(15)&q(37)&q(63)&q(4)&q(14)&q(47)&q(20)&q(21)&q(38)&q(53)&q(23)&q(45)&q(46)&q(55)&q(28)&q(5)&q(60)&q(18)&q(11)&q(59)&q(41)&q(42)&q(3)&q(52)&q(10)&q(25)&q(27)&q(49)&q(17)&q(57)&q(44)&q(50)&q(35)&q(26)&q(33)&q(1)&q(2)&q(51)&q(58)&q(19);
        kkey_10<=q(23)&q(47)&q(28)&q(38)&q(13)&q(45)&q(29)&q(5)&q(31)&q(53)&q(14)&q(20)&q(30)&q(63)&q(7)&q(37)&q(54)&q(4)&q(39)&q(61)&q(62)&q(6)&q(15)&q(21)&q(9)&q(34)&q(27)&q(44)&q(57)&q(58)&q(19)&q(1)&q(26)&q(41)&q(43)&q(2)&q(33)&q(10)&q(60)&q(3)&q(51)&q(42)&q(49)&q(17)&q(18)&q(36)&q(11)&q(35);
        kkey_11<=q(39)&q(63)&q(15)&q(54)&q(29)&q(61)&q(45)&q(21)&q(47)&q(4)&q(30)&q(7)&q(46)&q(14)&q(23)&q(53)&q(5)&q(20)&q(55)&q(12)&q(13)&q(22)&q(31)&q(37)&q(25)&q(50)&q(43)&q(60)&q(10)&q(11)&q(35)&q(17)&q(42)&q(57)&q(59)&q(18)&q(49)&q(26)&q(9)&q(19)&q(36)&q(58)&q(2)&q(33)&q(34)&q(52)&q(27)&q(51);
        kkey_12<=q(55)&q(14)&q(31)&q(5)&q(45)&q(12)&q(61)&q(37)&q(63)&q(20)&q(46)&q(23)&q(62)&q(30)&q(39)&q(4)&q(21)&q(7)&q(6)&q(28)&q(29)&q(38)&q(47)&q(53)&q(41)&q(3)&q(59)&q(9)&q(26)&q(27)&q(51)&q(33)&q(58)&q(10)&q(44)&q(34)&q(2)&q(42)&q(25)&q(35)&q(52)&q(11)&q(18)&q(49)&q(50)&q(1)&q(43)&q(36);
        kkey_13<=q(6)&q(30)&q(47)&q(21)&q(61)&q(28)&q(12)&q(53)&q(14)&q(7)&q(62)&q(39)&q(13)&q(46)&q(55)&q(20)&q(37)&q(23)&q(22)&q(15)&q(45)&q(54)&q(63)&q(4)&q(57)&q(19)&q(44)&q(25)&q(42)&q(43)&q(36)&q(49)&q(11)&q(26)&q(60)&q(50)&q(18)&q(58)&q(41)&q(51)&q(1)&q(27)&q(34)&q(2)&q(3)&q(17)&q(59)&q(52);
        kkey_14<=q(22)&q(46)&q(63)&q(37)&q(12)&q(15)&q(28)&q(4)&q(30)&q(23)&q(13)&q(55)&q(29)&q(62)&q(6)&q(7)&q(53)&q(39)&q(38)&q(31)&q(61)&q(5)&q(14)&q(20)&q(10)&q(35)&q(60)&q(41)&q(58)&q(59)&q(52)&q(2)&q(27)&q(42)&q(9)&q(3)&q(34)&q(11)&q(57)&q(36)&q(17)&q(43)&q(50)&q(18)&q(19)&q(33)&q(44)&q(1);
        kkey_15<=q(38)&q(62)&q(14)&q(53)&q(28)&q(31)&q(15)&q(20)&q(46)&q(39)&q(29)&q(6)&q(45)&q(13)&q(22)&q(23)&q(4)&q(55)&q(54)&q(47)&q(12)&q(21)&q(30)&q(7)&q(26)&q(51)&q(9)&q(57)&q(11)&q(44)&q(1)&q(18)&q(43)&q(58)&q(25)&q(19)&q(50)&q(27)&q(10)&q(52)&q(33)&q(59)&q(3)&q(34)&q(35)&q(49)&q(60)&q(17);
        kkey_16<=q(46)&q(5)&q(22)&q(61)&q(7)&q(39)&q(23)&q(28)&q(54)&q(47)&q(37)&q(14)&q(53)&q(21)&q(30)&q(31)&q(12)&q(63)&q(62)&q(55)&q(20)&q(29)&q(38)&q(15)&q(34)&q(59)&q(17)&q(2)&q(19)&q(52)&q(9)&q(26)&q(51)&q(3)&q(33)&q(27)&q(58)&q(35)&q(18)&q(60)&q(41)&q(36)&q(11)&q(42)&q(43)&q(57)&q(1)&q(25);
    end process;


    P2 : process(sel,kkey_1,kkey_2,kkey_3,kkey_4,kkey_5,kkey_6,kkey_7,kkey_8,kkey_9,kkey_10,kkey_11,kkey_12,kkey_13,kkey_14,kkey_15,kkey_16)
    begin
        if (sel(0)='0') then
            s0_0 <= kkey_1;
            s0_1 <= kkey_3;
            s0_2 <= kkey_5;
            s0_3 <= kkey_7;
            s0_4 <= kkey_9;
            s0_5 <= kkey_11;
            s0_6 <= kkey_13;
            s0_7 <= kkey_15;
        else
            s0_0 <= kkey_2;
            s0_1 <= kkey_4;
            s0_2 <= kkey_6;
            s0_3 <= kkey_8;
            s0_4 <= kkey_10;
            s0_5 <= kkey_12;
            s0_6 <= kkey_14;
            s0_7 <= kkey_16;
        end if;
    end process;


    P3 : process(sel,s0_0,s0_1,s0_2,s0_3,s0_4,s0_5,s0_6,s0_7)
    begin
        if (sel(1)='0') then
            s1_0 <= s0_0;
            s1_1 <= s0_2;
            s1_2 <= s0_4;
            s1_3 <= s0_6;
        else
            s1_0 <= s0_1;
            s1_1 <= s0_3;
            s1_2 <= s0_5;
            s1_3 <= s0_7;
        end if;
    end process;


    P4 : process(sel,s1_0,s1_1,s1_2,s1_3)
    begin
        if (sel(2)='0') then
            s2_0 <= s1_0;
            s2_1 <= s1_2;
        else
            s2_0 <= s1_1;
            s2_1 <= s1_3;
        end if;
    end process;


    P5 : process(sel,s2_0,s2_1)
    begin
        if (sel(3)='0') then
            subkey <= s2_0;
        else
            subkey <= s2_1;
        end if;
    end process;


end simple;


--------------------------------------------------------------------------
------------------------------------------------------ SUBS_1 ------------
--------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity subs_1 is
    port (
        entree : in  std_logic_vector(5 downto 0);
        sortie : out std_logic_vector(3 downto 0)
    );
end;


---------- Architecture subs_1 ---------- 
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of subs_1 is
begin
    P6 : process(entree)
    begin
        case entree is
            when "000000" => sortie<="1110";
            when "000001" => sortie<="0000";
            when "000010" => sortie<="0100";
            when "000011" => sortie<="1111";
            when "000100" => sortie<="1101";
            when "000101" => sortie<="0111";
            when "000110" => sortie<="0001";
            when "000111" => sortie<="0100";
            when "001000" => sortie<="0010";
            when "001001" => sortie<="1110";
            when "001010" => sortie<="1111";
            when "001011" => sortie<="0010";
            when "001100" => sortie<="1011";
            when "001101" => sortie<="1101";
            when "001110" => sortie<="1000";
            when "001111" => sortie<="0001";
            when "010000" => sortie<="0011";
            when "010001" => sortie<="1010";
            when "010010" => sortie<="1010";
            when "010011" => sortie<="0110";
            when "010100" => sortie<="0110";
            when "010101" => sortie<="1100";
            when "010110" => sortie<="1100";
            when "010111" => sortie<="1011";
            when "011000" => sortie<="0101";
            when "011001" => sortie<="1001";
            when "011010" => sortie<="1001";
            when "011011" => sortie<="0101";
            when "011100" => sortie<="0000";
            when "011101" => sortie<="0011";
            when "011110" => sortie<="0111";
            when "011111" => sortie<="1000";
            when "100000" => sortie<="0100";
            when "100001" => sortie<="1111";
            when "100010" => sortie<="0001";
            when "100011" => sortie<="1100";
            when "100100" => sortie<="1110";
            when "100101" => sortie<="1000";
            when "100110" => sortie<="1000";
            when "100111" => sortie<="0010";
            when "101000" => sortie<="1101";
            when "101001" => sortie<="0100";
            when "101010" => sortie<="0110";
            when "101011" => sortie<="1001";
            when "101100" => sortie<="0010";
            when "101101" => sortie<="0001";
            when "101110" => sortie<="1011";
            when "101111" => sortie<="0111";
            when "110000" => sortie<="1111";
            when "110001" => sortie<="0101";
            when "110010" => sortie<="1100";
            when "110011" => sortie<="1011";
            when "110100" => sortie<="1001";
            when "110101" => sortie<="0011";
            when "110110" => sortie<="0111";
            when "110111" => sortie<="1110";
            when "111000" => sortie<="0011";
            when "111001" => sortie<="1010";
            when "111010" => sortie<="1010";
            when "111011" => sortie<="0000";
            when "111100" => sortie<="0101";
            when "111101" => sortie<="0110";
            when "111110" => sortie<="0000";
            when others   => sortie<="1101";
        end case;
    end process;


end simple;




--------------------------------------------------------------------------
------------------------------------------------------ SUBS_2 ------------
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity subs_2 is
    port (
        entree : in  std_logic_vector(5 downto 0);
        sortie : out std_logic_vector(3 downto 0)
    );
end;


---------- Architecture subs_2 ---------- 
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of subs_2 is
begin
    P7 : process(entree)
    begin
        case entree is
            when "000000" => sortie<="1111";
            when "000001" => sortie<="0011";
            when "000010" => sortie<="0001";
            when "000011" => sortie<="1101";
            when "000100" => sortie<="1000";
            when "000101" => sortie<="0100";
            when "000110" => sortie<="1110";
            when "000111" => sortie<="0111";
            when "001000" => sortie<="0110";
            when "001001" => sortie<="1111";
            when "001010" => sortie<="1011";
            when "001011" => sortie<="0010";
            when "001100" => sortie<="0011";
            when "001101" => sortie<="1000";
            when "001110" => sortie<="0100";
            when "001111" => sortie<="1110";
            when "010000" => sortie<="1001";
            when "010001" => sortie<="1100";
            when "010010" => sortie<="0111";
            when "010011" => sortie<="0000";