baud.vhd

vhdl 很好用于串行通信. 三个模快,发生时钟,发送和 接收过程

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity baud is

port(clk:in std_logic;
	reset:in std_logic;
	rxd_fa:in std_logic;
			
	data:out std_logic_vector(7 downto 0);
	txd:out std_logic);
end entity baud;

architecture Behavioral of baud is

constant clk_div_number: integer:=(2000000/(9600 *16 *2));---7
signal clk_div:std_logic_vector(4 downto 0);
signal bclk:std_logic;

signal ldsr:std_logic;
signal ldrb:std_logic;
signal fe:std_logic;
signal sclk:std_logic;
signal data1:std_logic_vector(9 downto 1);
signal rxbuffer:std_logic_vector(7 downto 0);

signal rxd_sync:std_logic;
signal rxd_shift:std_logic_vector(7 downto 0);
signal rxcnt8:integer range 0 to 7;
signal rxd_cnt:integer range 0 to 9;

signal txd_shift:std_logic_vector(7 downto 0);
signal txcnt8:integer range 0 to 7;
signal txd_cnt:integer range 0 to 7;
type states is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15);
signal state,next_state:states;
begin

	mbclk_procedure:process(clk,reset)
	begin
		if  reset='0' then
			clk_div<=(others=>'0');
			bclk<='0';
		elsif clk 'event and clk='1' then     --rising_edge(clk) then
			if(clk_div=clk_div_number) then
				clk_div<=(others=>'0');
				bclk<= not bclk;
			else
				clk_div<=clk_div+'1';
			end if;
		end if;
	end process mbclk_procedure;
	
	filter:process(bclk,reset)
	variable samples:std_logic_vector(1 downto 0);
	begin
		if(reset='0') then
			samples:="11";
			rxd_sync<='1';
		elsif bclk 'event and bclk='1' then--rising_edge(bclk_tmp) then
			samples(1):=samples(0);
			samples(0):=rxd_fa;
			if samples="00" then
				rxd_sync<='0';
			elsif samples="11" then
				rxd_sync<='1';
			end if;
		end if;
	end process filter;

	
	fsm:process(bclk)
	begin
		if bclk 'event and bclk='1' then
			state<=next_state;
		end if;
	end process fsm;

	receiver:process(state)
	begin
		case state is
			when s0=>              --接受机所有