📄 baud.rpt
字号:
_EQ040 = reset & rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & rxd_cnt0 &
!rxd_cnt1 & !rxd_cnt2 & rxd_cnt3 & rxd_shift7
# _LC9_D2 & _X026;
_X026 = EXP( reset & rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & rxd_cnt0 &
!rxd_cnt1 & !rxd_cnt2 & rxd_cnt3);
-- Node name is ':6'
-- Equation name is '_LC10_B3', type is buried
_LC10_B3 = DFFE( _EQ041 $ GND, bclk, VCC, VCC, VCC);
_EQ041 = reset & rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & rxd_cnt0 &
!rxd_cnt1 & !rxd_cnt2 & rxd_cnt3 & rxd_shift6
# _LC10_B3 & _X026;
_X026 = EXP( reset & rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & rxd_cnt0 &
!rxd_cnt1 & !rxd_cnt2 & rxd_cnt3);
-- Node name is ':8'
-- Equation name is '_LC11_B3', type is buried
_LC11_B3 = DFFE( _EQ042 $ GND, bclk, VCC, VCC, VCC);
_EQ042 = reset & rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & rxd_cnt0 &
!rxd_cnt1 & !rxd_cnt2 & rxd_cnt3 & rxd_shift5
# _LC11_B3 & _X026;
_X026 = EXP( reset & rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & rxd_cnt0 &
!rxd_cnt1 & !rxd_cnt2 & rxd_cnt3);
-- Node name is ':10'
-- Equation name is '_LC9_B3', type is buried
_LC9_B3 = DFFE( _EQ043 $ GND, bclk, VCC, VCC, VCC);
_EQ043 = reset & rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & rxd_cnt0 &
!rxd_cnt1 & !rxd_cnt2 & rxd_cnt3 & rxd_shift4
# _LC9_B3 & _X026;
_X026 = EXP( reset & rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & rxd_cnt0 &
!rxd_cnt1 & !rxd_cnt2 & rxd_cnt3);
-- Node name is ':12'
-- Equation name is '_LC9_C1', type is buried
_LC9_C1 = DFFE( _EQ044 $ GND, bclk, VCC, VCC, VCC);
_EQ044 = reset & rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & rxd_cnt0 &
!rxd_cnt1 & !rxd_cnt2 & rxd_cnt3 & rxd_shift3
# _LC9_C1 & _X026;
_X026 = EXP( reset & rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & rxd_cnt0 &
!rxd_cnt1 & !rxd_cnt2 & rxd_cnt3);
-- Node name is ':14'
-- Equation name is '_LC10_C1', type is buried
_LC10_C1 = DFFE( _EQ045 $ GND, bclk, VCC, VCC, VCC);
_EQ045 = reset & rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & rxd_cnt0 &
!rxd_cnt1 & !rxd_cnt2 & rxd_cnt3 & rxd_shift2
# _LC10_C1 & _X026;
_X026 = EXP( reset & rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & rxd_cnt0 &
!rxd_cnt1 & !rxd_cnt2 & rxd_cnt3);
-- Node name is ':16'
-- Equation name is '_LC11_C1', type is buried
_LC11_C1 = DFFE( _EQ046 $ GND, bclk, VCC, VCC, VCC);
_EQ046 = reset & rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & rxd_cnt0 &
!rxd_cnt1 & !rxd_cnt2 & rxd_cnt3 & rxd_shift1
# _LC11_C1 & _X026;
_X026 = EXP( reset & rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & rxd_cnt0 &
!rxd_cnt1 & !rxd_cnt2 & rxd_cnt3);
-- Node name is ':18'
-- Equation name is '_LC13_B3', type is buried
_LC13_B3 = DFFE( _EQ047 $ GND, bclk, VCC, VCC, VCC);
_EQ047 = reset & rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & rxd_cnt0 &
!rxd_cnt1 & !rxd_cnt2 & rxd_cnt3 & rxd_shift0
# _LC13_B3 & _X026;
_X026 = EXP( reset & rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & rxd_cnt0 &
!rxd_cnt1 & !rxd_cnt2 & rxd_cnt3);
-- Node name is ':20'
-- Equation name is '_LC8_C1', type is buried
_LC8_C1 = DFFE( _EQ048 $ _EQ049, bclk, VCC, reset, VCC);
_EQ048 = _LC8_C1 & _X027;
_X027 = EXP( txcnt160 & txcnt161 & txcnt162 & txcnt163);
_EQ049 = !_LC1_A5 & txcnt160 & txcnt161 & txcnt162 & txcnt163;
-- Node name is '~956~1'
-- Equation name is '~956~1', location is LC10_D2, type is buried.
-- synthesized logic cell
_LC10_D2 = LCELL( _EQ050 $ GND);
_EQ050 = rxd_shift7 & rxd_sync
# !rxd_shift7 & !rxd_sync;
-- Node name is '~965~1'
-- Equation name is '~965~1', location is LC12_D2, type is buried.
-- synthesized logic cell
_LC12_D2 = LCELL( _EQ051 $ GND);
_EQ051 = rxd_shift6 & rxd_shift7
# !rxd_shift6 & !rxd_shift7;
-- Node name is '~974~1'
-- Equation name is '~974~1', location is LC4_B3, type is buried.
-- synthesized logic cell
_LC4_B3 = LCELL( _EQ052 $ GND);
_EQ052 = rxd_shift5 & rxd_shift6
# !rxd_shift5 & !rxd_shift6;
-- Node name is '~983~1'
-- Equation name is '~983~1', location is LC5_B3, type is buried.
-- synthesized logic cell
_LC5_B3 = LCELL( _EQ053 $ GND);
_EQ053 = rxd_shift4 & rxd_shift5
# !rxd_shift4 & !rxd_shift5;
-- Node name is '~992~1'
-- Equation name is '~992~1', location is LC14_C1, type is buried.
-- synthesized logic cell
_LC14_C1 = LCELL( _EQ054 $ GND);
_EQ054 = rxd_shift3 & rxd_shift4
# !rxd_shift3 & !rxd_shift4;
-- Node name is '~1001~1'
-- Equation name is '~1001~1', location is LC15_C1, type is buried.
-- synthesized logic cell
_LC15_C1 = LCELL( _EQ055 $ GND);
_EQ055 = rxd_shift2 & rxd_shift3
# !rxd_shift2 & !rxd_shift3;
-- Node name is '~1019~1'
-- Equation name is '~1019~1', location is LC6_B3, type is buried.
-- synthesized logic cell
_LC6_B3 = LCELL( _EQ056 $ GND);
_EQ056 = rxd_shift0 & rxd_shift1
# !rxd_shift0 & !rxd_shift1;
-- Node name is '~1127~1'
-- Equation name is '~1127~1', location is LC7_B3, type is buried.
-- synthesized logic cell
_LC7_B3 = LCELL( _EQ057 $ GND);
_EQ057 = rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163
# rxcnt160 & rxcnt161 & rxcnt162 & !rxd_cnt1 & !rxd_cnt2 &
!rxd_cnt3;
-- Node name is '~1127~2'
-- Equation name is '~1127~2', location is LC8_B3, type is buried.
-- synthesized logic cell
_LC8_B3 = LCELL( _EQ058 $ GND);
_EQ058 = rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & rxd_cnt0
# rxcnt160 & rxcnt161 & rxcnt162 & rxcnt163 & !rxd_cnt1 &
!rxd_cnt2 & !rxd_cnt3;
-- Node name is '~1854~1'
-- Equation name is '~1854~1', location is LC1_A5, type is buried.
-- synthesized logic cell
_LC1_A5 = LCELL( _EQ059 $ GND);
_EQ059 = txd_cnt0 & !txd_shift0
# txd_cnt2 & !txd_shift0
# txd_cnt1 & !txd_cnt3 & !txd_shift0
# !txd_cnt1 & txd_cnt3 & !txd_shift0
# txd_cnt0 & !txd_cnt1 & !txd_cnt2 & !txd_cnt3;
-- Node name is ':1891'
-- Equation name is '_LC1_B5', type is buried
_LC1_B5 = LCELL( _EQ060 $ GND);
_EQ060 = _LC1_B5 & reset;
Project Information d:\exep\baud.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX9000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:03
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:06
-------------------------- --------
Total Time 00:00:12
Memory Allocated
-----------------
Peak memory allocated during compilation = 8,037K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -