📄 baud.rpt
字号:
D: 0 14 0 0 0 14
Total: 15 14 13 15 2 59
Device-Specific Information: d:\exep\baud.rpt
baud
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC Row Col Primitive Code Total Shared n/a INP FBK OUT FBK Name
182 - - -- INPUT G 0 0 0 0 0 0 0 clk
153 - - -- INPUT 0 0 0 0 0 0 49 reset
183 - - -- INPUT 0 0 0 0 0 0 2 rxd
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\exep\baud.rpt
baud
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC Row Col Primitive Code Total Shared n/a INP FBK OUT FBK Name
124 - B -- OUTPUT 0 0 0 0 1 0 0 rbuf0
131 - C -- OUTPUT 0 0 0 0 1 0 0 rbuf1
130 - C -- OUTPUT 0 0 0 0 1 0 0 rbuf2
129 - C -- OUTPUT 0 0 0 0 1 0 0 rbuf3
34 - B -- OUTPUT 0 0 0 0 1 0 0 rbuf4
126 - B -- OUTPUT 0 0 0 0 1 0 0 rbuf5
125 - B -- OUTPUT 0 0 0 0 1 0 0 rbuf6
135 - D -- OUTPUT 0 0 0 0 1 0 0 rbuf7
29 - C -- OUTPUT 0 0 0 0 1 0 0 txd
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\exep\baud.rpt
baud
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
IOC LC Row Col Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 9 D 02 DFFE t 1 1 0 1 10 1 0 :4
- 10 B 03 DFFE t 1 1 0 1 10 1 0 :6
- 11 B 03 DFFE t 1 1 0 1 10 1 0 :8
- 9 B 03 DFFE t 1 1 0 1 10 1 0 :10
- 9 C 01 DFFE t 1 1 0 1 10 1 0 :12
- 10 C 01 DFFE t 1 1 0 1 10 1 0 :14
- 11 C 01 DFFE t 1 1 0 1 10 1 0 :16
- 13 B 03 DFFE t 1 1 0 1 10 1 0 :18
- 8 C 01 DFFE t 1 0 0 1 6 1 0 :20
- 9 A 04 TFFE + t 0 0 0 1 4 0 4 clk_div4 (:22)
- 8 A 04 TFFE + t 0 0 0 1 3 0 5 clk_div3 (:23)
- 7 A 04 TFFE + t 0 0 0 1 4 0 5 clk_div2 (:24)
- 6 A 04 DFFE + t 0 0 0 1 4 0 5 clk_div1 (:25)
- 5 A 04 DFFE + t 0 0 0 1 4 0 5 clk_div0 (:26)
- 1 A 04 TFFE + t 0 0 0 1 5 0 42 bclk (:27)
- 14 D 02 DFFE t 1 0 0 2 2 0 5 rxd_sync (:28)
- 13 D 02 TFFE t 2 2 0 1 10 0 3 rxd_shift7 (:29)
- 8 D 02 TFFE t 2 2 0 1 10 0 3 rxd_shift6 (:30)
- 3 B 03 TFFE t 2 2 0 1 10 0 3 rxd_shift5 (:31)
- 2 B 03 TFFE t 2 2 0 1 10 0 3 rxd_shift4 (:32)
- 13 C 01 TFFE t 2 2 0 1 10 0 3 rxd_shift3 (:33)
- 12 C 01 TFFE t 2 2 0 1 10 0 3 rxd_shift2 (:34)
- 3 C 01 TFFE t 4 2 0 1 10 0 2 rxd_shift1 (:35)
- 12 B 03 TFFE t 2 2 0 1 10 0 2 rxd_shift0 (:36)
- 7 D 02 DFFE t 3 3 0 1 9 0 21 rxcnt163 (:37)
- 6 D 02 DFFE t 3 2 0 1 8 0 22 rxcnt162 (:38)
- 5 D 02 TFFE t 1 1 0 1 7 0 23 rxcnt161 (:39)
- 4 D 02 DFFE t 0 0 0 1 6 0 24 rxcnt160 (:40)
- 3 D 02 TFFE t 0 0 0 1 8 0 23 rxd_cnt3 (:41)
- 2 D 02 TFFE t 0 0 0 1 7 0 24 rxd_cnt2 (:42)
- 1 D 02 TFFE t 1 0 0 1 8 0 24 rxd_cnt1 (:43)
- 1 B 03 DFFE t 0 0 0 1 3 0 24 rxd_cnt0 (:44)
- 10 A 04 TFFE t 4 2 0 1 10 0 1 txd_shift6 (:46)
- 11 A 04 TFFE t 4 2 0 1 10 0 1 txd_shift5 (:47)
- 12 A 04 TFFE t 4 2 0 1 10 0 1 txd_shift4 (:48)
- 13 A 04 TFFE t 4 2 0 1 10 0 1 txd_shift3 (:49)
- 14 A 04 TFFE t 4 2 0 1 10 0 1 txd_shift2 (:50)
- 15 A 04 TFFE t 4 2 0 1 10 0 1 txd_shift1 (:51)
- 4 A 04 TFFE t 4 2 0 1 10 0 1 txd_shift0 (:52)
- 4 C 01 TFFE t 0 0 0 1 4 0 12 txcnt163 (:53)
- 7 C 01 TFFE t 0 0 0 1 3 0 13 txcnt162 (:54)
- 6 C 01 DFFE t 0 0 0 1 2 0 14 txcnt161 (:55)
- 5 C 01 TFFE t 0 0 0 1 1 0 15 txcnt160 (:56)
- 2 A 04 TFFE t 0 0 0 1 8 0 10 txd_cnt3 (:57)
- 2 C 01 TFFE t 0 0 0 1 7 0 11 txd_cnt2 (:58)
- 3 A 04 TFFE t 0 0 0 1 8 0 11 txd_cnt1 (:59)
- 1 C 01 TFFE t 1 1 0 1 8 0 11 txd_cnt0 (:60)
- 11 D 02 DFFE t 0 0 0 2 1 0 1 samples0 (:222)
- 10 D 02 SOFT s t 0 0 0 0 2 0 1 ~956~1
- 12 D 02 SOFT s t 0 0 0 0 2 0 1 ~965~1
- 4 B 03 SOFT s t 0 0 0 0 2 0 1 ~974~1
- 5 B 03 SOFT s t 0 0 0 0 2 0 1 ~983~1
- 14 C 01 SOFT s t 0 0 0 0 2 0 1 ~992~1
- 15 C 01 SOFT s t 0 0 0 0 2 0 1 ~1001~1
- 6 B 03 SOFT s t 0 0 0 0 2 0 1 ~1019~1
- 7 B 03 SOFT s t 0 0 0 0 7 0 1 ~1127~1
- 8 B 03 SOFT s t 0 0 0 0 8 0 1 ~1127~2
- 1 A 05 SOFT s t 1 0 1 0 5 0 1 ~1854~1
- 1 B 05 AND2 t 0 0 0 1 0 0 1 :1891
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\exep\baud.rpt
baud
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
FastTrack
Row Interconnect Input Pins Output Pins Bidir Pins
A: 11/ 96( 11%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 15/ 96( 15%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 18/ 96( 18%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
D: 5/ 96( 5%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 7/48( 14%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
02: 8/48( 16%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
03: 2/48( 4%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
04: 3/48( 6%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
05: 2/48( 4%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
Device-Specific Information: d:\exep\baud.rpt
baud
** EQUATIONS **
clk : INPUT;
reset : INPUT;
rxd : INPUT;
-- Node name is ':27' = 'bclk'
-- Equation name is 'bclk', location is LC1_A4, type is buried.
bclk = TFFE( _EQ001, GLOBAL( clk), reset, VCC, VCC);
_EQ001 = !clk_div0 & clk_div1 & clk_div2 & !clk_div3 & !clk_div4;
-- Node name is ':26' = 'clk_div0'
-- Equation name is 'clk_div0', location is LC5_A4, type is buried.
clk_div0 = DFFE( _EQ002 $ VCC, GLOBAL( clk), reset, VCC, VCC);
_EQ002 = clk_div1 & clk_div2 & !clk_div3 & !clk_div4
# clk_div0;
-- Node name is ':25' = 'clk_div1'
-- Equation name is 'clk_div1', location is LC6_A4, type is buried.
clk_div1 = DFFE( _EQ003 $ VCC, GLOBAL( clk), reset, VCC, VCC);
_EQ003 = !clk_div0 & !clk_div1
# clk_div0 & clk_div1
# !clk_div0 & clk_div2 & !clk_div3 & !clk_div4;
-- Node name is ':24' = 'clk_div2'
-- Equation name is 'clk_div2', location is LC7_A4, type is buried.
clk_div2 = TFFE( _EQ004, GLOBAL( clk), reset, VCC, VCC);
_EQ004 = clk_div0 & clk_div1
# clk_div1 & clk_div2 & !clk_div3 & !clk_div4;
-- Node name is ':23' = 'clk_div3'
-- Equation name is 'clk_div3', location is LC8_A4, type is buried.
clk_div3 = TFFE( _EQ005, GLOBAL( clk), reset, VCC, VCC);
_EQ005 = clk_div0 & clk_div1 & clk_div2;
-- Node name is ':22' = 'clk_div4'
-- Equation name is 'clk_div4', location is LC9_A4, type is buried.
clk_div4 = TFFE( _EQ006, GLOBAL( clk), reset, VCC, VCC);
_EQ006 = clk_div0 & clk_div1 & clk_div2 & clk_div3;
-- Node name is 'rbuf0'
-- Equation name is 'rbuf0', type is output
rbuf0 = _LC13_B3;
-- Node name is 'rbuf1'
-- Equation name is 'rbuf1', type is output
rbuf1 = _LC11_C1;
-- Node name is 'rbuf2'
-- Equation name is 'rbuf2', type is output
rbuf2 = _LC10_C1;
-- Node name is 'rbuf3'
-- Equation name is 'rbuf3', type is output
rbuf3 = _LC9_C1;
-- Node name is 'rbuf4'
-- Equation name is 'rbuf4', type is output
rbuf4 = _LC9_B3;
-- Node name is 'rbuf5'
-- Equation name is 'rbuf5', type is output
rbuf5 = _LC11_B3;
-- Node name is 'rbuf6'
-- Equation name is 'rbuf6', type is output
rbuf6 = _LC10_B3;
-- Node name is 'rbuf7'
-- Equation name is 'rbuf7', type is output
rbuf7 = _LC9_D2;
-- Node name is ':40' = 'rxcnt160'
-- Equation name is 'rxcnt160', location is LC4_D2, type is buried.
rxcnt160 = DFFE( _EQ007 $ VCC, bclk, reset, VCC, VCC);
_EQ007 = !rxd_cnt0 & !rxd_cnt1 & !rxd_cnt2 & !rxd_cnt3 & rxd_sync
# rxcnt160;
-- Node name is ':39' = 'rxcnt161'
-- Equation name is 'rxcnt161', location is LC5_D2, type is buried.
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