📄 baud.rpt
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Project Information d:\exep\baud.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/04/2005 14:08:12
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
BAUD
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
baud EPM9320ARC208-10 3 9 0 59 35 18 %
User Pins: 3 9 0
Project Information d:\exep\baud.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information d:\exep\baud.rpt
** FILE HIERARCHY **
|lpm_add_sub:142|
|lpm_add_sub:142|addcore:adder|
|lpm_add_sub:142|addcore:adder|addcore:adder0|
|lpm_add_sub:142|altshift:result_ext_latency_ffs|
|lpm_add_sub:142|altshift:carry_ext_latency_ffs|
|lpm_add_sub:142|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:436|
|lpm_add_sub:436|addcore:adder|
|lpm_add_sub:436|addcore:adder|addcore:adder0|
|lpm_add_sub:436|altshift:result_ext_latency_ffs|
|lpm_add_sub:436|altshift:carry_ext_latency_ffs|
|lpm_add_sub:436|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:528|
|lpm_add_sub:528|addcore:adder|
|lpm_add_sub:528|addcore:adder|addcore:adder0|
|lpm_add_sub:528|altshift:result_ext_latency_ffs|
|lpm_add_sub:528|altshift:carry_ext_latency_ffs|
|lpm_add_sub:528|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:710|
|lpm_add_sub:710|addcore:adder|
|lpm_add_sub:710|addcore:adder|addcore:adder0|
|lpm_add_sub:710|altshift:result_ext_latency_ffs|
|lpm_add_sub:710|altshift:carry_ext_latency_ffs|
|lpm_add_sub:710|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1353|
|lpm_add_sub:1353|addcore:adder|
|lpm_add_sub:1353|addcore:adder|addcore:adder0|
|lpm_add_sub:1353|altshift:result_ext_latency_ffs|
|lpm_add_sub:1353|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1353|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1441|
|lpm_add_sub:1441|addcore:adder|
|lpm_add_sub:1441|addcore:adder|addcore:adder0|
|lpm_add_sub:1441|altshift:result_ext_latency_ffs|
|lpm_add_sub:1441|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1441|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1522|
|lpm_add_sub:1522|addcore:adder|
|lpm_add_sub:1522|addcore:adder|addcore:adder0|
|lpm_add_sub:1522|altshift:result_ext_latency_ffs|
|lpm_add_sub:1522|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1522|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\exep\baud.rpt
baud
***** Logic for device 'baud' compiled without errors.
Device: EPM9320ARC208-10
Device Options:
Turbo Bit = ON
Security Bit = OFF
User Code = ffff
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S
E E E E E E E E E E E E V E E E E E E E E E E E E E E E V E E E E E E E E E E E E E E E V E E
R R R R R R R R R R R R C R R R R R R R R R R R R R R R C R R R R R R R R R R R R R R R C R R
V V G V V V V V V V V V V C V V V V V G V V V V V r c V V V V V C V V V V V G V V V V V V V V V V C V V
E E N E E E E E E E E E E I E E E E E N E E E E E x l E E E E E I E E E E E N E E E E E E E E E E I E E
D D D D D D D D D D D D D O D D D D D D D D D D D d k D D D D D O D D D D D D D D D D D D D D D D O D D
----------------------------------------------------------------------------------------------------------_
/ 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
RESERVED | 1 156 | RESERVED
RESERVED | 2 155 | RESERVED
RESERVED | 3 154 | RESERVED
GND | 4 153 | reset
VCCIO | 5 152 | GND
N.C. | 6 151 | N.C.
N.C. | 7 150 | N.C.
N.C. | 8 149 | N.C.
N.C. | 9 148 | VCCINT
VCCINT | 10 147 | N.C.
N.C. | 11 146 | N.C.
N.C. | 12 145 | N.C.
N.C. | 13 144 | N.C.
GND | 14 143 | GND
N.C. | 15 142 | N.C.
N.C. | 16 141 | N.C.
N.C. | 17 140 | N.C.
N.C. | 18 139 | VCCINT
VCCINT | 19 138 | VCCIO
GND | 20 137 | RESERVED
RESERVED | 21 136 | RESERVED
RESERVED | 22 135 | rbuf7
RESERVED | 23 134 | RESERVED
GND | 24 133 | GND
VCCIO | 25 132 | GND
RESERVED | 26 131 | rbuf1
RESERVED | 27 EPM9320ARC208-10 130 | rbuf2
RESERVED | 28 129 | rbuf3
txd | 29 128 | VCCINT
VCCINT | 30 127 | VCCIO
GND | 31 126 | rbuf5
RESERVED | 32 125 | rbuf6
RESERVED | 33 124 | rbuf0
rbuf4 | 34 123 | RESERVED
GND | 35 122 | GND
VCCIO | 36 121 | GND
RESERVED | 37 120 | RESERVED
RESERVED | 38 119 | RESERVED
RESERVED | 39 118 | GND
RESERVED | 40 117 | RESERVED
GND | 41 116 | GND
GND | 42 115 | GND
GND | 43 114 | GND
GND | 44 113 | GND
VCCINT | 45 112 | VCCINT
GND | 46 111 | VCCIO
GND | 47 110 | GND
^VPP | 48 109 | N.C.
#TMS | 49 108 | #TDO
RESERVED | 50 107 | RESERVED
RESERVED | 51 106 | RESERVED
RESERVED | 52 105 | RESERVED
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R R V R R R R R R R R R R G R R R R R V R R R R R # # R R R R R G R R R R R V R R R R R R R R R R G R R
E E C E E E E E E E E E E N E E E E E C E E E E E T T E E E E E N E E E E E C E E E E E E E E E E N E E
S S C S S S S S S S S S S D S S S S S C S S S S S C D S S S S S D S S S S S C S S S S S S S S S S D S S
E E I E E E E E E E E E E E E E E E I E E E E E K I E E E E E E E E E E I E E E E E E E E E E E E
R R O R R R R R R R R R R R R R R R O R R R R R R R R R R R R R R R O R R R R R R R R R R R R
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\exep\baud.rpt
baud
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External Shareable
Block Logic Cells Driven Driven Clocks Presets Interconnect Expanders
A4 15/16( 93%) 3/16( 18%) 3/16( 18%) 0/2 0/2 8/33( 24%) 16/16(100%)
A5 1/16( 6%) 1/16( 6%) 0/16( 0%) 0/2 0/2 5/33( 15%) 1/16( 6%)
B3 13/16( 81%) 2/16( 12%) 4/16( 25%) 0/2 0/2 11/33( 33%) 3/16( 18%)
B5 1/16( 6%) 1/16( 6%) 0/16( 0%) 0/2 0/2 1/33( 3%) 0/16( 0%)
C1 15/16( 93%) 7/16( 43%) 4/16( 25%) 0/2 0/2 14/33( 42%) 7/16( 43%)
D2 14/16( 87%) 8/16( 50%) 1/16( 6%) 0/2 0/2 4/33( 12%) 8/16( 50%)
Total dedicated input pins used: 3/4 ( 75%)
Total I/O pins used: 9/128 ( 7%)
Total logic cells used: 59/320 ( 18%)
Total shareable expanders used: 34/320 ( 10%)
Total Turbo logic cells used: 59/320 ( 18%)
Total shareable expanders not available (n/a): 1/320 ( 0%)
Average fan-in: 8.45
Total fan-in: 499
Total input pins required: 3
Total input I/O cell registers required: 0
Total output pins required: 9
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total logic cells required: 59
Total flipflops required: 48
Total product terms required: 211
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 27
Total packed registers required: 0
Synthesized logic cells: 10/ 320 ( 3%)
Logic Cell Counts
Column: 01 02 03 04 05 Total
A: 0 0 0 15 1 16
B: 0 0 13 0 1 14
C: 15 0 0 0 0 15
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