📄 sdram.txt
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sram is
port (
CLK66 : in std_logic;
-- System Clock
RESET : in std_logic;
-- System Reset
CLK165 : in std_logic;
-- tv dataout System Clock
COM_VH : in STD_LOGIC;
--TV
COM_VH_B : in STD_LOGIC;
--TV
VRST_B : in STD_LOGIC;
--TV
HRST_B : in STD_LOGIC;
--TV
RE_BANK : in STD_LOGIC_VECTOR (1 DOWNTO 0);
--READ SDRAM BANK ADDRESS
WR_BANK : in STD_LOGIC_VECTOR (1 DOWNTO 0);
--WRITE SDRAM BANK ADDRESS
WR_SDROWADD : in STD_LOGIC_VECTOR (8 DOWNTO 0);
--WRITE SDRAM ROW ADDRESS
RE_SDROWADD : in STD_LOGIC_VECTOR (8 DOWNTO 0);
--READ SDRAM ROW ADDRESS
WR_DATAIN : in std_logic_vector(15 downto 0);
--SDRAM datain from VGA DP_RAM
RE_ROMADD : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
--READ ROM DATA ADDRESS
DQ : INOUT std_logic_vector(15 downto 0);
-- SDRAM data bus --WRITE
SA : out std_logic_vector(12 downto 0);
--OUT FOR SDRAM address
BA : out std_logic_vector(1 downto 0);
--OUT FOR SDRAM bank address
DATA_OUT : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0);
--TV OUTPUT TO D/A
CKE : out std_logic;
-- SDRAM clock enable
DQML : out std_logic;
-- SDRAM DQML AND DQMH
DQMH : out std_logic;
-- SDRAM DQML AND DQMH
CS_N : out std_logic;
-- SDRAM chip selects
RAS_N : out std_logic;
-- SDRAM RAS
CAS_N : out std_logic;
-- SDRAM CAS
RW : out std_logic;
-- SDRAM CAS
WE_N : out std_logic
-- SDRAM WE_N
);
end sram;
architecture RTL of sram is
signal SA0,SA1 : std_logic_vector(12 downto 0);
------ OUT FOR SDRAM address
signal CMD1,CMD0,CMD : std_logic_vector(2 downto 0);
signal DQM,INI_END : std_logic;
signal INI_ST : std_logic;
signal WR_SDBUS_EN : std_logic;
------ sdram databus select.
signal RE_COLADD : std_logic_vector(5 downto 0);
------ READ SDRAM COLUMN ADD HIGH 6BIT
signal WR_COLADD : std_logic_vector(6 downto 0);
------ WRITE SDRAM ADDRESS 10bit HIGH 7BIT .ROW 13BIT
------ ROW ADDRESS IS 13BIT =="000"&WR_COLADD&"000";
signal WR_COLADD2 : std_logic_vector(2 downto 0); ----------&"000"
------ WR_COLADD&WR_COLADD2 IS THE READ ROM ADDRESS
------ WR_COLADD IS FOR SDRAM WRITE SDRAM ADDRESS
signal TV_REG10,TV_REG11 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal TV_REG12,TV_REG13 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal TV_REG14,TV_REG15 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal TV_REG16,TV_REG17 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal TV_REG20,TV_REG21 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal TV_REG22,TV_REG23 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal TV_REG24,TV_REG25 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal TV_REG26,TV_REG27 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal TVREG_SEL : std_logic;
SIGNAL RW_START : std_logic;
--'1'for READ SDRAM,'0'FOR WRITE SDRAM
begin
DQML <=DQM;
DQMH <=DQM;
CS_N <='0'; -- SDRAM chip selects
CKE <='1';
WE_N <= CMD(0); -- SDRAM RAS
CAS_N <= CMD(1); -- SDRAM CAS
RAS_N <= CMD(2); -- SDRAM WE_N
----RAS_N & CAS_N & WE_N
-----CMD0(2 DOWNTO 0) AND CMD1(2 DOWNTO 0);
WR_SDBUS_EN <=(NOT RW_START);
CMD <=CMD0 WHEN INI_END='0' ELSE CMD1;
SA <=SA0 WHEN INI_END='0' ELSE SA1;
DQ <=WR_DATAIN WHEN WR_SDBUS_EN='1' ELSE (OTHERS=>'Z');
p0005: PROCESS(CLK66,reset)
VARIABLE TEMP : std_logic_vector(34 downto 0);
VARIABLE TT : INTEGER RANGE 0 TO 255;
VARIABLE T_T : STD_LOGIC;
BEGIN
if reset='0' then
TEMP :="00000000000000000000000000000000001";
T_T:='0';
elsIF CLK66'event and CLK66='1' then
T_T := TEMP(34);
TEMP(34 DOWNTO 1):=TEMP(33 DOWNTO 0);
TEMP(0):=T_T;
IF TEMP(34)='1' THEN
IF TT>= 0 AND TT <=240 THEN
TT :=TT+1;
INI_ST <='0';
ELSE
INI_ST <='1';
END IF;
END IF;
END IF;
END PROCESS;
p0001: process(CLK66, RESET,INI_END,COM_VH_B)
variable temp1 : std_logic_vector(5 downto 0);
VARIABLE RW_TEMP : std_logic;
VARIABLE TV_SEL_TEMP : std_logic;
begin
if RESET ='0'OR INI_END='0'OR COM_VH_B='1' then
temp1 := (others => '0');
RW_START <= '0' ;
RW <= '0' ;
RW_TEMP := '0' ;
TVREG_SEL <= '0' ;
elsif CLK66'event and CLK66='1' then
if temp1(4 downto 0)="00000" then
RW_START <=RW_TEMP;
RW <=RW_TEMP;
RW_TEMP :=NOT RW_TEMP;
end if;
if temp1="000000" then
TVREG_SEL <=TV_SEL_TEMP;
TV_SEL_TEMP :=NOT TV_SEL_TEMP;
end if;
temp1 := temp1+1;
end if;
end process;
------------------------------------------------------------------------
-- Issue the Initialization command first.
P_INI: Process(CLK66, RESET)
VARIABLE TEMP : std_logic_vector(28 downto 0);
begin
if RESET = '0' then
SA0 <= (others => '0');
TEMP :="00000000000000000000000000001";
CMD0 <="111";
INI_END <='0';
elsif CLK66'EVENT AND CLK66='1' then
IF INI_ST='1' THEN
IF TEMP(28)='0' THEN
TEMP(28 DOWNTO 1):=TEMP(27 DOWNTO 0);
TEMP(0):='0';
IF TEMP(5)='1' THEN
SA0(10) <='1';
ELSIF TEMP(6)='1' THEN
CMD0<="010";
------ -----PRECHARGE
ELSIF TEMP(9)='1' THEN
CMD0<="111";
------ -----PRECHARGE
SA0(10) <='0';
ELSIF TEMP(10)='1'OR TEMP(18)='1' THEN
CMD0<="001";
---AUTO REFRESH ,FIRST AND SECOND
SA0(10) <='0';
ELSIF TEMP(25)='1' THEN
CMD0<="111";
------ -----PRECHARGE
SA0 <="0000000110011";
ELSIF TEMP(26)='1' THEN
CMD0<="000";
------NOP COMMAND
SA0 <="0000000110011";
---A12-A0--13 bits
ELSE
CMD0<="111";
SA0 <= (others => '0');
END IF;
INI_END <='0';
ELSE
INI_END <='1';
CMD0 <="111";
SA0 <= (others => '0');
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
RE_SD_COL_ADDRESS: Process(RW_START, RESET,INI_END,COM_VH_B,VRST_B)
------READ SDRAM ADDRESS
begin
if RESET = '0'OR INI_END='0' OR COM_VH_B='1' OR VRST_B='1' then
RE_COLADD <="110101";
-- ;(OTHERS=>'0')
elsif RW_START'EVENT AND RW_START='1' then
RE_COLADD <=RE_COLADD-1; --- +1;
end if;
end process;
----------------------------------------------------------
WR_SD_COL_ADDRESS: Process(RW_START, RESET,INI_END,COM_VH_B,VRST_B)
----WRITE SDRAM ADDRESS
begin
if RESET = '0'OR INI_END='0'OR COM_VH_B='1' OR VRST_B='1' then
WR_COLADD<=(OTHERS=>'0');
elsif RW_START'EVENT AND RW_START='0' then
WR_COLADD<=WR_COLADD+1; ------1===8 ,coloumn address.
end if;
end process;
RE_ROMADD <= WR_COLADD & WR_COLADD2;
------------------------------------------------------------------------------
P_READ_WRITE: Process(CLK66, RESET,INI_END)
VARIABLE RE_T : std_logic_vector(19 downto 0);
VARIABLE WR_T : std_logic_vector(15 downto 0);
VARIABLE TEMP : std_logic_vector(2 downto 0);
begin
if RESET = '0' OR INI_END='0' then
SA1 <= (others => '0');
BA <= (others => '0');
TEMP := (others => '0');
WR_COLADD2 <= (others => '0');
RE_T :="00000000000000000001";
WR_T :="0000000000000001";
CMD1 <="111";
TV_REG10 <= (others => '0');
TV_REG11 <= (others => '0');
TV_REG12 <= (others => '0');
TV_REG13 <= (others => '0');
TV_REG14 <= (others => '0');
TV_REG15 <= (others => '0');
TV_REG16 <= (others => '0');
TV_REG17 <= (others => '0');
TV_REG20 <= (others => '0');
TV_REG21 <= (others => '0');
TV_REG22 <= (others => '0');
TV_REG23 <= (others => '0');
TV_REG24 <= (others => '0');
TV_REG25 <= (others => '0');
TV_REG26 <= (others => '0');
TV_REG27 <= (others => '0');
elsif CLK66'EVENT AND CLK66='1' then
IF ( RW_START='1' ) THEN ----------READ COMMANDAND INI_END='1'
WR_T :="0000000000000001";
DQM<='0';
IF RE_T(19)='0' THEN
RE_T(19 DOWNTO 1):=RE_T(18 DOWNTO 0);
RE_T(0):='0';
IF ( COM_VH_B='0' ) THEN --
IF RE_T(1)='1' THEN
CMD1<="111"; ------ACTIVE and en0='0'
SA1 <="0000"&RE_SDROWADD;
BA<= RE_BANK;
ELSIF RE_T(2)='1' THEN
CMD1<="011"; ------ACTIVE
SA1 <="0000"&RE_SDROWADD;
BA<= RE_BANK;
ELSIF RE_T(4)='1' THEN
CMD1<="101";
------READ COMMAND and en0='0')
SA1(8 DOWNTO 0)<=RE_COLADD&"000";
SA1(10) <='0';
----READ WITHOUT AUTO PRECHARGE
BA<= RE_BANK;
ELSIF RE_T(8)='1' THEN
--------READ DATA 1
CMD1<="111";
------NOP COMMAND
CASE TVREG_SEL IS
WHEN '0' => TV_REG10<= DQ;-- RE_DATA_TEMP;
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