12.txt

for lattice s vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;

entity mGen is
	PORT(Wclk1,Wclk2,clk:IN STD_LOGIC;
             Cscoeff,CsPR:IN STD_LOGIC;
		data_A:in std_logic_vector(7 downto 0);
		data_B:in std_logic_vector(6 downto 0);
		m_out:out std_logic);
end mGen;

architecture behavioral of mGen is
	signal coeff_reg:std_logic_vector(7 downto 1):=(others=>'0');
	signal phase_reg:std_logic_vector(7 downto 0):=(others=>'0');
	signal dl:std_logic:='0';
begin
	coeff_reg:PORCESS(wck1,CsCoeff)
	begin
	if(wclk1'event and wclk1='1') then
		if CsCoeff='1' then
			coeff_reg<=data_B;
		end if;
	end if;
end process coeff_reg;

phase_reg:PROCESS(Wclk2,phase_reg)
begin
	if(Wclk2'event and Wclk2='1')then
	if CsPR='1' then
	   phase_reg<=data_A;
	end if;
	end if;
end process phase_reg;

PNG_m:PROCESS(clk,dl)
begin
   if(clk'event and clk='1')then
	phase_reg(7)<=dl;
	phase_reg(6)<=phase_reg(7);
	phase_reg(5)<=phase_reg(6);
	phase_reg(4)<=phase_reg(5);
	phase_reg(3)<=phase_reg(4);
	phase_reg(2)<=phase_reg(3);
	phase_reg(1)<=phase_reg(2);
	phase_reg(0)<=phase_reg(1);
   end if;
   end process PNG_m;
dl<=phase_reg(0) xor (phase_reg(1) and coeff_reg(7))
	xor(phase_reg(2) and coeff_reg(6))	
  	xor(phase_reg(3) and coeff_reg(5))
	xor(phase_reg(4) and coeff_reg(4))
	xor(phase_reg(5) and coeff_reg(3))
	xor(phase_reg(6) and coeff_reg(2))
	xor(phase_reg(7) and coeff_reg(1));
	m_out<=phase_reg(0);

end behavioral;