fpdramc.vhd

SDRAM控制器,对SDRAM进行页写和对SDRAM进行页读的快速读写。是一个很好的SDRAM控制器

-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2001 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Permission:
--
--   Lattice Semiconductor grants permission to use this code for use
--   in synthesis for any Lattice programmable logic product.  Other
--   use of this code, including the selling or duplication of any
--   portion is strictly prohibited.
--
-- Disclaimer:
--
--   This VHDL or Verilog source code is intended as a design reference
--   which illustrates how these types of functions can be implemented.
--   It is the user's responsibility to verify their design for
--   consistency and functionality through the use of formal
--   verification methods.  Lattice Semiconductor provides no warranty
--   regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--           
--                     Lattice Semiconductor Corporation
--                     5555 NE Moore Court
--                     Hillsboro, OR 97214
--                     U.S.A
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--                     TEL: 1-800-Lattice (USA and Canada)
--                          408-826-6000 (other locations)
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--                     web: http://www.latticesemi.com/
--                     email: [e-mail]
--
-- --------------------------------------------------------------------
--
-- This is the top-level module of the FPM DRAM controller reference
-- design.
--
-- --------------------------------------------------------------------
--
-- --------------------------------------------------------------------
--
-- Revision History :
-- --------------------------------------------------------------------
--   Ver  :| Author            :| Mod. Date :| Changes Made:
--   V1.0 :| K.L.              :| 09/16/98  :| Pre-Release
--   V2.0 :| J.R.              :| 12/17/01  :| Converted to VHDL
-- --------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity fpdram is port(
  a                       : in    std_logic_vector(23 downto 0);  -- address bus
  asb                     : in    std_logic;                      -- address strobe
  siz1, siz0              : in    std_logic;                      -- indicates transfer size
  clk                     : in    std_logic;                      -- input clock
  rwb                     : in    std_logic;                      -- read/write strobe (0 ==> write)
  resetb                  : in    std_logic;                      -- reset input, active LOW

  ras1o, ras2o            : out   std_logic;                      -- Row Address Strobes for 2 banks
  ucaso, lcaso            : out   std_logic;                      -- Upper and Lower Column Address Strobes
  weo                     : out   std_logic;                      -- DRAM Write strobe
  dsack1o, dsack0o        : out   std_logic;                      -- Data Size/Acknowledge signals
  ma                      : out   std_logic_vector(9 downto 0));  -- Multiplexed DRAM address
end;

architecture behavioral of fpdram is
-- Component Declarations
  component sm port(                                                      -- State Machine
    clk                     : in    std_logic; 
    dramsel                 : in    std_logic;
    resetb                  : in    std_logic;
    page_hit                : in    std_logic;
    bnk1,bnk2               : in    std_logic;
    upd, lod                : in    std_logic;
    rwb                     : in    std_logic;
    ras1,ras2               : out   std_logic;
    ucas,lcas               : out   std_logic;
    we                      : out   std_logic;
    dsack1                  : out   std_logic;
    dsack0                  : out   std_logic);
  end component;
  
  component decoder  port(                                                -- Address Decoder
    a23, a22, a21, a0       : in    std_logic;
    asb, siz1, siz0         : in    std_logic;
    dsack1                  : in    std_logic;
    resetb                  : in    std_logic;
    bnk1, bnk2              : out   std_logic; 
    upd, lod                : out   std_logic; 
    dramsel                 : out   std_logic;
    page_hit                : out   std_logic);
  end component;
  
  component mux port (                                                    -- Address Mux
    a                       : in std_logic_vector(20 downto 1);
    ras1, ras2              : in std_logic;
    ma                      : out std_logic_vector(9 downto 0));
  end component;

-- Define internal signals that interconnect the four components.
  signal  dramsel                 : std_logic;
  signal  page_hit                : std_logic;
  signal  bank1, bank2            : std_logic;
  signal  upd, lod                : std_logic;
  signal  ras1, ras2              : std_logic;
  signal  ds1, ds0                : std_logic;

begin
  
  -- Component Instantiations
  
  u1: decoder port map(a23 => a(23), a22 => a(22), a21 => a(21), a0 => a(0),
                       asb => asb, siz1 => siz1, siz0 => siz0, dsack1 => ds1,
                       resetb => resetb, bnk1 => bank1,
                       bnk2 => bank2, upd => upd, lod => lod, dramsel => dramsel,
                       page_hit => page_hit);
  
  
  u2: sm port map(clk => clk, dramsel => dramsel, resetb => resetb, page_hit => page_hit,
                  bnk1 => bank1, bnk2 => bank2, upd => upd, lod => lod, rwb => rwb,
                  ras1 => ras1, ras2 => ras2, ucas => ucaso, lcas => lcaso, we => weo,
                  dsack1 => ds1, dsack0 => ds0);
  
  u3: mux port map(a => a(20 downto 1), ras1 => ras1, ras2 => ras2, ma => ma);
  
  
  -- Connect those signals that also tie to external ports to those ports

  ras1o   <= ras1;
  ras2o   <= ras2;
  dsack1o <= ds1;
  dsack0o <= ds0;

end behavioral;