mux.vhd

SDRAM控制器,对SDRAM进行页写和对SDRAM进行页读的快速读写。是一个很好的SDRAM控制器

-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2001 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Permission:
--
--   Lattice Semiconductor grants permission to use this code for use
--   in synthesis for any Lattice programmable logic product.  Other
--   use of this code, including the selling or duplication of any
--   portion is strictly prohibited.
--
-- Disclaimer:
--
--   This VHDL or Verilog source code is intended as a design reference
--   which illustrates how these types of functions can be implemented.
--   It is the user's responsibility to verify their design for
--   consistency and functionality through the use of formal
--   verification methods.  Lattice Semiconductor provides no warranty
--   regarding the use or functionality of this code.
--
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--                     Lattice Semiconductor Corporation
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-- --------------------------------------------------------------------
--
-- This is the DRAM multiplexer module of the FPM DRAM controller reference
-- design.
--
-- --------------------------------------------------------------------
--
-- --------------------------------------------------------------------
--
-- Revision History :
-- --------------------------------------------------------------------
--   Ver  :| Author            :| Mod. Date :| Changes Made:
--   V1.0 :| K.L.              :| 09/16/98  :| Pre-Release
--   V2.0 :| J.R.              :| 12/17/01  :| Converted to VHDL
-- --------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity mux is port (
        a               : in std_logic_vector(20 downto 1);     -- cpu address inputs
        ras1, ras2      : in std_logic;                         -- dram control inputs
        ma              : out std_logic_vector(9 downto 0));    -- muxed address outputs
end mux;

architecture behavioral of mux is

signal rasbdly          : std_logic;               -- The logical OR of the two RAS signals
signal dd_rasb          : std_logic;               -- delayed rasbdly 

-- Node preservation attributes.
--  Two levels of attributes are required: One for the synthesis tool and another for the fitter.
--  'OPT' is defined for the fitter engine.
--  'PRESERVE_SIGNAL' is defined for Exemplar.
--  'SYN_KEEP' is defined for Synplify.
ATTRIBUTE PRESERVE_SIGNAL : BOOLEAN;  
ATTRIBUTE OPT : string;
ATTRIBUTE SYN_KEEP : BOOLEAN;

ATTRIBUTE PRESERVE_SIGNAL OF dd_rasb : SIGNAL IS TRUE;
ATTRIBUTE SYN_KEEP OF dd_rasb : SIGNAL IS TRUE;
ATTRIBUTE OPT OF dd_rasb : SIGNAL IS "KEEP";
ATTRIBUTE PRESERVE_SIGNAL OF rasbdly : SIGNAL IS TRUE;
ATTRIBUTE SYN_KEEP OF rasbdly : SIGNAL IS TRUE;
ATTRIBUTE OPT OF rasbdly : SIGNAL IS "KEEP";


begin

rasbdly <= not(ras1 and ras2);                     -- Asserted when either ras1 or ras2 is asserted
                                                   
dd_rasb <= rasbdly;                                -- dd_rasb is the mux select line for the address
                                                   -- mux.  This is just a delayed version of rasbdly. 
                                                   -- Needed to add an additional level of delay   
                                                   -- to satisfy the row address hold time requirement 
                                                   -- of the DRAMs.

ma      <= a(10 downto 1) when dd_rasb = '1' else  -- column address during RAS active
           a(20 downto 11);

end behavioral;