fpdramtb.vhd

SDRAM控制器,对SDRAM进行页写和对SDRAM进行页读的快速读写。是一个很好的SDRAM控制器

-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2001 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Permission:
--
--   Lattice Semiconductor grants permission to use this code for use
--   in synthesis for any Lattice programmable logic product.  Other
--   use of this code, including the selling or duplication of any
--   portion is strictly prohibited.
--
-- Disclaimer:
--
--   This VHDL or Verilog source code is intended as a design reference
--   which illustrates how these types of functions can be implemented.
--   It is the user's responsibility to verify their design for
--   consistency and functionality through the use of formal
--   verification methods.  Lattice Semiconductor provides no warranty
--   regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--           
--                     Lattice Semiconductor Corporation
--                     5555 NE Moore Court
--                     Hillsboro, OR 97214
--                     U.S.A
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--                     TEL: 1-800-Lattice (USA and Canada)
--                          408-826-6000 (other locations)
--
--                     web: http://www.latticesemi.com/
--                     email: [e-mail]
--
-- --------------------------------------------------------------------
--
-- This is the testbench module of the FPM DRAM controller reference
-- design.
--
-- --------------------------------------------------------------------
--
-- --------------------------------------------------------------------
--
-- Revision History :
-- --------------------------------------------------------------------
--   Ver  :| Author            :| Mod. Date :| Changes Made:
--   V2.0 :| J.R.              :| 12/17/01  :| Initial Version
-- --------------------------------------------------------------------

LIBRARY ieee;
LIBRARY generics;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE generics.components.ALL;

ENTITY fpdramtb IS
END fpdramtb;

ARCHITECTURE behavior OF fpdramtb IS 

  COMPONENT fpdram
  PORT(
    clk     : IN std_logic;
    a       : IN std_logic_vector(23 downto 0);
    asb     : IN std_logic;
    siz1    : IN std_logic;
    siz0    : IN std_logic;
    rwb     : IN std_logic;
    resetb  : IN std_logic;          
    ras1o   : OUT std_logic;
    ras2o   : OUT std_logic;
    ucaso   : OUT std_logic;
    lcaso   : OUT std_logic;
    weo     : OUT std_logic;
    dsack1o : OUT std_logic;
    dsack0o : OUT std_logic;
    ma      : OUT std_logic_vector(9 downto 0)
    );
  END COMPONENT;

  SIGNAL clk      : std_logic := '1';
  SIGNAL a        : std_logic_vector(23 downto 0):= "000000000000000000000000";
  SIGNAL asb      : std_logic := '1';
  SIGNAL siz1     : std_logic := '1';
  SIGNAL siz0     : std_logic := '1';
  SIGNAL rwb      : std_logic := '1';
  SIGNAL resetb   : std_logic := '1';
  SIGNAL ras1o    : std_logic;
  SIGNAL ras2o    : std_logic;
  SIGNAL ucaso    : std_logic;
  SIGNAL lcaso    : std_logic;
  SIGNAL weo      : std_logic;
  SIGNAL dsack1o  : std_logic;
  SIGNAL dsack0o  : std_logic;
  SIGNAL ma       : std_logic_vector(9 downto 0);

BEGIN

  uut: fpdram PORT MAP(
    a       => a,
    asb     => asb,
    siz1    => siz1,
    siz0    => siz0,
    clk     => clk,
    rwb     => rwb,
    resetb  => resetb,
    ras1o   => ras1o,
    ras2o   => ras2o,
    ucaso   => ucaso,
    lcaso   => lcaso,
    weo     => weo,
    dsack1o => dsack1o,
    dsack0o => dsack0o,
    ma      => ma
  );

-- Generate the 25MHz (40 ns) system clock
  clk_gen: process
  begin
    wait for 20 ns;
    clk <= not (clk);
  end process;


  tb : PROCESS
  BEGIN
    wait for 40 ns;
    -- reset the controller
    resetb <= '0';
    wait for 80 ns;
    resetb <= '1';
    wait  for 30 ns;
    -- ***** Accesses to Bank 1 *****
    -- Random Mode Word READ
    a <= "000111100001100000000000";
    wait for 20 ns;
    asb <= '0';
    siz0 <= '0';
    wait for 120 ns;
    asb <= '1';
    siz0 <= '1';
    wait for 20 ns;
    -- Random Mode Word Write
    a <= "000111100000100000000000"; -- write to different page
    rwb <= '0';
    wait for 20 ns;
    asb <= '0';
    siz0 <= '0';
    wait for 160 ns;
    asb <= '1';
    siz0 <= '1';
    wait for 80 ns;
    rwb  <= '1';
    wait for 20 ns;
    -- Random Mode Upper Byte READ
    a <= "000111100001100000000000";
    rwb <= '1';
    wait for 20 ns ;
    asb <= '0';
    siz1 <= '0';
    wait for 120 ns;
    asb <= '1';
    siz1 <= '1';
    wait for 20 ns;
    -- Random Mode Lower Byte Write
    a <= "000111100000100000000001"; -- write to different page
    rwb <= '0';
    wait for 20 ns;
    asb <= '0';
    siz1 <= '0';
    wait for 160 ns;
    asb <= '1';
    siz1 <= '1';
    wait for 80 ns;
    rwb  <= '1';
    wait for 20 ns;
    -- ***** Accesses to Bank 2 *****
    -- Random Mode Word READ
    a <= "001111100001100000000000"; 
    wait  for 20 ns;
    asb <= '0';
    siz0 <= '0';
    wait for 120 ns;
    asb <= '1';
    siz0 <= '1';
    wait for 20 ns;
    -- Random Mode Word Write
    a <= "001111100000100000000000"; -- write to different page in the same bank
    rwb <= '0';
    wait for 20 ns;
    asb <= '0';
    siz0 <= '0';
    wait for 160 ns;
    asb <= '1';
    siz0 <= '1';
    wait for 80 ns;
    rwb  <= '1';
    wait for 20 ns;
    -- Random Mode Upper Byte READ
    a <= "001111100001100000000000"; 
    wait  for 20 ns;
    asb <= '0';
    siz1 <= '0';
    wait for 120 ns;
    asb <= '1';
    siz1 <= '1';
    wait for 20 ns;
    -- Random Mode Lower Byte Write
    a <= "001111100000100000000001"; -- write to different page in the same bank
    rwb <= '0';
    wait for 20 ns;
    asb <= '0';
    siz1 <= '0';
    wait for 160 ns;
    asb <= '1';
    siz1 <= '1';
    wait for 80 ns;
    rwb  <= '1';
    wait for 20 ns;

    -- Start Page mode access to bank 1, 1st access is in random mode, assert A22 to indicate
    -- to the controller that page mode accesses will follow.
    -- Subsequent accesses are in page mode, terminate page mode by deasserting A22
    -- on the last access.
    a <= "010110011001100000000000";
    rwb <= '0';
    wait for 20 ns;
    asb <= '0';
    siz0 <= '0';
    wait for 120 ns;
    asb <= '1';
    wait for 20 ns;
    a <= "010110011001100000001000";
    wait for 20 ns;
    asb <= '0';
    wait for 80 ns;
    asb <= '1';
    wait for 20 ns;
    a <= "000110011001100000010000";        -- For this access deassert A22 to terminate page mode cycles
    wait for 20 ns;
    asb <= '0';
    wait for 80 ns;
    asb <= '1';
    siz0 <= '1';
    wait for 140 ns;

    -- Start Page mode access to bank 2, 1st access is in random mode, assert A22 to indicate
    -- to the controller that page mode accesses will follow.
    -- Subsequent accesses are in page mode, terminate page mode by deasserting A22
    -- on the last access.
    a <= "011110011001100000000000";
    rwb <= '1';
    wait for 20 ns;
    asb <= '0';
    siz0 <= '0';
    wait for 120 ns;
    asb <= '1';
    wait for 20 ns;
    a <= "011110011001100000001000";
    wait for 20 ns;
    asb <= '0';
    wait for 80 ns;
    asb <= '1';
    wait for 20 ns;
    a <= "001110011001100000010000";        -- For this access, deassert A22 to terminate page mode cycles
    wait for 20 ns;
    asb <= '0';
    wait for 80 ns;
    asb <= '1';
    siz0 <= '1';
    wait for 12940 ns;                      -- Wait until the same clock cycle that the refreq is asserted 
                                            -- to start another access.  Do this to make sure that the 
                                            -- refresh cycle has priority over the normal access.
                                            -- After the refresh cycle is run, the normal access will run.
    a <= "000111100000100000000000";        -- Do a write cycle
    rwb <= '0';
    wait for 20 ns;
    asb <= '0';
    siz0 <= '0';
    wait for 400 ns;
    asb <= '1';
    siz0 <= '1';
    wait for 100 ns;
    wait;

  END PROCESS;
END;