decoder.vhd

SDRAM控制器,对SDRAM进行页写和对SDRAM进行页读的快速读写。是一个很好的SDRAM控制器

-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2001 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Permission:
--
--   Lattice Semiconductor grants permission to use this code for use
--   in synthesis for any Lattice programmable logic product.  Other
--   use of this code, including the selling or duplication of any
--   portion is strictly prohibited.
--
-- Disclaimer:
--
--   This VHDL or Verilog source code is intended as a design reference
--   which illustrates how these types of functions can be implemented.
--   It is the user's responsibility to verify their design for
--   consistency and functionality through the use of formal
--   verification methods.  Lattice Semiconductor provides no warranty
--   regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--           
--                     Lattice Semiconductor Corporation
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--                     Hillsboro, OR 97214
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--                     TEL: 1-800-Lattice (USA and Canada)
--                          408-826-6000 (other locations)
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--                     web: http://www.latticesemi.com/
--                     email: [e-mail]
--
-- --------------------------------------------------------------------
--
-- This is the decoder module of the FPM DRAM controller reference
-- design.
--
-- --------------------------------------------------------------------
--
-- --------------------------------------------------------------------
--
-- Revision History :
-- --------------------------------------------------------------------
--   Ver  :| Author            :| Mod. Date :| Changes Made:
--   V1.0 :| K.L.              :| 09/16/98  :| Pre-Release
--   V2.0 :| J.R.              :| 12/17/01  :| Converted to VHDL
-- --------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity decoder is port(

        a23, a22, a21, a0       : in    std_logic;
        asb, siz1, siz0         : in    std_logic;
        dsack1                  : in    std_logic;
        resetb                  : in    std_logic;

        bnk1, bnk2              : out   std_logic;  
        upd, lod                : out   std_logic;  
        dramsel                 : out   std_logic;
        page_hit                : out   std_logic); 
end decoder;

architecture behavioral of decoder is 

signal bt2wd_e                  : std_logic;    -- Byte to word (even) transfer
signal bt2wd_o                  : std_logic;    -- Byte to word (odd) transfer
signal wd2wd                    : std_logic;    -- Word to word transfer
signal lwd2wd                   : std_logic;    -- Long word to word transfer

begin

----design note ---------------
-- The equation 'dramsel' in this design uses the condition that
--  the upper 8 bit address lines (a31-a22) of 68340 MPU is configured
--  as a parallel port or interrupt acknowledge signals.
-- If the system requires the use of upper address area, the equation
-- should be written as following.
-- dramarea = [!a31 & !a30 & !a29 & !a28 & !a27 & !a26
--           & !a25 & !a24 & !a23 & !a22];


------------------------
--** address decoding ** 
------------------------

dramsel <= '1' when (a23 = '0' and asb = '0') else
           '0';
bnk1 <= (not a23) and (not a21) and (not asb);  -- decoded for 0000000 - 01fffff
                                                -- and         0400000 - 05fffff

bnk2 <= (not a23) and a21 and (not asb);        -- Decoded for 0200000 - 03fffff
                                                -- and         0600000 - 07fffff


-------------------------------
---- Memory Page Detection ----
-------------------------------

-- A page mode access is started/continued when A22 = 1 at the
-- start of a CPU bus cycle.

pgdetec: process (resetb, asb)
begin
        if (resetb = '0') then
          page_hit <= '0';
        elsif (asb'event and asb = '0') then
          if (a22 = '1') then
            page_hit <= '1';
          else
            page_hit <= '0';
          end if;
        end if;
end process;


--------------------------------------------------
--** cpu-to-memory data transfer size interface **
--------------------------------------------------

-- dram controller transfer modes
-- support byte to word, word to word, long word to word modes

bt2wd_e <= (not asb) and (not siz1) and siz0       and (not a0) and (not dsack1);
bt2wd_o <= (not asb) and (not siz1) and siz0       and a0       and (not dsack1);
wd2wd   <= (not asb) and siz1       and (not siz0) and (not a0) and (not dsack1);
lwd2wd  <= (not asb) and (not siz1) and (not siz0) and (not a0) and (not dsack1);


--// ------------------------------------------------------------------------------
--// for other peripheral interface,  not used for dram operations
--//    bt2bt           =       [!asb & !siz1 &  siz0 &  dsack1 & !dsack0];
--//    wd2bt           =       [!asb &  siz1 & !siz0 & !a0 &  dsack1 & !dsack0];
--//    lwd2bt          =       [!asb & !siz1 & !siz0 & !a0 &  dsack1 & !dsack0];
--// ------------------------------------------------------------------------------

upd <=  '1' when (bt2wd_e = '1' or wd2wd = '1' or lwd2wd = '1') else
        '0';
                 
lod <=  '1' when (bt2wd_o = '1' or wd2wd = '1' or lwd2wd = '1') else
        '0';

end behavioral;