options.ref

来自「openaccess与verilog互相转化时所用的源代码」· REF 代码 · 共 223 行

******************************************************************************
* No Explode, No EMH
******************************************************************************
Contents of options_design.top.myview
    Contents of module level1
            Term: 'l1_out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'l1_out'
        	Position:	1
            Term: 'l1_in[31:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	32
        	Net:		'l1_in[31:0]'
        	Position:	0
            Net: 'l1_reg' (ModScalarNet)
            Net: 'l1_out' (ModScalarNet)
            Net: 'l1_in[31:0]' (ModBusNet)
    Contents of module level2A
            Term: 'l2Aio[1:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	2
        	Net:		'l2Aio[1:0]'
        	Position:	0
            Net: 'globalNet' (ModScalarNet)
            Global:	true
            Net: 'myTieHigh' (ModScalarNet)
            SigType:	tieHi
            Global:	true
            Net: 'myTieLow' (ModScalarNet)
            SigType:	tieLo
            Global:	true
            Net: '31*myTieLow,myTieHigh' (ModBundleNet)
            Net: 'l2Aio[1:0]' (ModBusNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	Master Cell Name:	level1
        	NumBits:		1
        ModInstTerm:
        	Net:	globalNet
        	Inst:	I1
	Posit:	1 (bound to 'l1_out')
        ModInstTerm:
        	Net:	31*myTieLow,myTieHigh
        	Inst:	I1
	Posit:	0 (bound to 'l1_in[31:0]')
    Contents of module level2B
            Term: 'l2Bio[1:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	2
        	Net:		'l2Bio[1:0]'
        	Position:	0
            Net: 'globalNet' (ModScalarNet)
            Global:	true
            Net: 'myTieLow' (ModScalarNet)
            SigType:	tieLo
            Global:	true
            Net: 'myTieHigh' (ModScalarNet)
            SigType:	tieHi
            Global:	true
            Net: 'myTieHigh,31*myTieLow' (ModBundleNet)
            Net: 'l2Bio[1:0]' (ModBusNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	Master Cell Name:	level1
        	NumBits:		1
        ModInstTerm:
        	Net:	globalNet
        	Inst:	I1
	Posit:	1 (bound to 'l1_out')
        ModInstTerm:
        	Net:	myTieHigh,31*myTieLow
        	Inst:	I1
	Posit:	0 (bound to 'l1_in[31:0]')
    Contents of TOP module top
            Net: 'myTieLow,myTieHigh' (ModBundleNet)
            Net: 'myTieLow' (ModScalarNet)
            SigType:	tieLo
            Global:	true
            Net: 'myTieHigh' (ModScalarNet)
            SigType:	tieHi
            Global:	true
            Net: 'myTieHigh,myTieLow' (ModBundleNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I2B
        	Master Cell Name:	level2B
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I1A
        	Master Cell Name:	level2A
        	NumBits:		1
        ModInstTerm:
        	Net:	myTieLow,myTieHigh
        	Inst:	I2B
	Posit:	0 (bound to 'l2Bio[1:0]')
        ModInstTerm:
        	Net:	myTieHigh,myTieLow
        	Inst:	I1A
	Posit:	0 (bound to 'l2Aio[1:0]')



User defined callback was used successfully.
Reader succeeded



******************************************************************************
* No Explode, EMH
******************************************************************************
Contents of options_designEMH.top.myview
    Contents of module level1
            Term: 'l1_out' (ModScalarTerm)
        	TermType:	output
        	NumBits:	1
        	Net:		'l1_out'
        	Position:	1
            Term: 'l1_in[31:0]' (ModBusTerm)
        	TermType:	input
        	NumBits:	32
        	Net:		'l1_in[31:0]'
        	Position:	0
            Net: 'l1_reg' (ModScalarNet)
            Net: 'l1_out' (ModScalarNet)
            Net: 'l1_in[31:0]' (ModBusNet)
    Contents of module level2A
            Term: 'l2Aio[1:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	2
        	Net:		'l2Aio[1:0]'
        	Position:	0
            Net: 'globalNet' (ModScalarNet)
            Global:	true
            Net: 'myTieHigh' (ModScalarNet)
            SigType:	tieHi
            Global:	true
            Net: 'myTieLow' (ModScalarNet)
            SigType:	tieLo
            Global:	true
            Net: '31*myTieLow,myTieHigh' (ModBundleNet)
            Net: 'l2Aio[1:0]' (ModBusNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	Master Cell Name:	level1
        	NumBits:		1
        ModInstTerm:
        	Net:	globalNet
        	Inst:	I1
	Posit:	1 (bound to 'l1_out')
        ModInstTerm:
        	Net:	31*myTieLow,myTieHigh
        	Inst:	I1
	Posit:	0 (bound to 'l1_in[31:0]')
    Contents of module level2B
            Term: 'l2Bio[1:0]' (ModBusTerm)
        	TermType:	inputOutput
        	NumBits:	2
        	Net:		'l2Bio[1:0]'
        	Position:	0
            Net: 'globalNet' (ModScalarNet)
            Global:	true
            Net: 'myTieLow' (ModScalarNet)
            SigType:	tieLo
            Global:	true
            Net: 'myTieHigh' (ModScalarNet)
            SigType:	tieHi
            Global:	true
            Net: 'myTieHigh,31*myTieLow' (ModBundleNet)
            Net: 'l2Bio[1:0]' (ModBusNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I1
        	Master Cell Name:	level1
        	NumBits:		1
        ModInstTerm:
        	Net:	globalNet
        	Inst:	I1
	Posit:	1 (bound to 'l1_out')
        ModInstTerm:
        	Net:	myTieHigh,31*myTieLow
        	Inst:	I1
	Posit:	0 (bound to 'l1_in[31:0]')
    Contents of TOP module top
            Net: 'myTieLow,myTieHigh' (ModBundleNet)
            Net: 'myTieLow' (ModScalarNet)
            SigType:	tieLo
            Global:	true
            Net: 'myTieHigh' (ModScalarNet)
            SigType:	tieHi
            Global:	true
            Net: 'myTieHigh,myTieLow' (ModBundleNet)
        ModInst:
        	Is Bound:		yes
        	InstName:		I2B
        	Master Cell Name:	level2B
        	NumBits:		1
        ModInst:
        	Is Bound:		yes
        	InstName:		I1A
        	Master Cell Name:	level2A
        	NumBits:		1
        ModInstTerm:
        	Net:	myTieLow,myTieHigh
        	Inst:	I2B
	Posit:	0 (bound to 'l2Bio[1:0]')
        ModInstTerm:
        	Net:	myTieHigh,myTieLow
        	Inst:	I1A
	Posit:	0 (bound to 'l2Aio[1:0]')



User defined callback was used successfully.
Reader succeeded