📄 verilog2oa.cpp
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// *****************************************************************************// *****************************************************************************// main.cpp//// This file contains the implementation of the standalone verilog2oa // application.//// *****************************************************************************// Except as specified in the OpenAccess terms of use of Cadence or Silicon// Integration Initiative, this material may not be copied, modified,// re-published, uploaded, executed, or istributed in any way, in any medium,// in whole or in part, without prior written permission from Cadence.//// Copyright 2003-2005 Cadence Design Systems, Inc.// All Rights Reserved.//// $Author: sailajad $// $Revision: 1.74 $// $Date: 2005/08/05 21:58:13 $// $State: Exp $// *****************************************************************************// *****************************************************************************#include "oaVerilog.h"#include "oaUtilApp.h"using namespace oa;using namespace oaUtil;using namespace oaVerilog;// *****************************************************************************// verilog2oaBuild// *****************************************************************************class verilog2oaBuild : public oaBuildInfo { verilog2oaBuild() : oaBuildInfo("verilog2oa", OA_BUILD_NAME, OA_BUILD_TIME, OA_BUILD_NUMBER) {} private: static verilog2oaBuild buildInfo;};// *****************************************************************************// oaVerilogInApp//// Application class to for a stand-alone application that uses the VerilogIn// component. This class does not appear in a header file because the// oaVeriogIn component is the public interface. See VerilogIn.h// *****************************************************************************class oaVerilogInApp : public oaUtil::TranslatorApp<ReaderOptions> { public: oaVerilogInApp(); oaBoolean validateArgs(); virtual void run(); private: VerilogIn reader; OptionsIn &options; Arg<ArgList> verilogOpt; Switch blackBoxOpt; Switch designPerModOpt; Arg<oaString> globalsOpt; Arg<ArgList> leafLibsOpt; Arg<ArgList> leafViewsOpt; Arg<oaString> tieHighOpt; Arg<oaString> tieLowOpt; Switch tolerateOpt; Arg<oaString> topOpt; Arg<oaString> viewOpt; Arg<oaString> viewTypeOpt; static const InputInfo input; static const OutputInfo output;};// *****************************************************************************// Initialize Static Data Members;// *****************************************************************************verilog2oaBuild verilog2oaBuild::buildInfo;const InputInfo oaVerilogInApp::input("Verilog", "IEEE 1364-2001");const OutputInfo oaVerilogInApp::output(FormatInfo::OpenAccess());// *****************************************************************************// oaVerilogInApp::oaVerilogInApp()//// This method is the constructor for the oaVerilogInApp.// *****************************************************************************oaVerilogInApp::oaVerilogInApp(): oaUtil::TranslatorApp<ReaderOptions>("Translates Verilog to OpenAccess"), reader(_msgs), options(reader.getOptions()), verilogOpt(_args, "verilog", "-verilog fileList", "Quoted list of input Verilog files"), blackBoxOpt(_args, "blackBox", "[-blackBox]", "Create separate designs for empty modules"), designPerModOpt(_args, "designPerMod", "[-designPerMod]", "Create separate design per Verilog module"), globalsOpt(_args, "globals", "[-globals module]", "Name of module that contains global nets", "globals"), leafLibsOpt(_args, "leafLibs", "[-leafLibs libList]", "List of libraries that contain leaf cells", ArgList(0)), leafViewsOpt(_args, "leafViews", "[-leafViews viewList]", "List of leaf view names", ArgList(0)), tieHighOpt(_args, "tieHigh", "[-tieHigh net]", "Tie high net name", "tie1"), tieLowOpt(_args, "tieLow", "[-tieLow net]", "Tie low net name", "tie0"), tolerateOpt(_args, "tolerate", "[-tolerate]", "Tolerate unimplemented features"), topOpt(_args, "top", "[-top module]", "Name of the top module", ""), viewOpt(_args, "view", "[-view name]", "Name of the view used to create new oaDesigns", "netlist"), viewTypeOpt(_args, "viewType", "[-viewType name]", "Name of the view type used to create new oaDesigns", "netlist"){}// *****************************************************************************// oaVerilogInApp::validateArgs()//// This method validates the command line arguments for the application.// *****************************************************************************oaBooleanoaVerilogInApp::validateArgs(){ oaVerilogNS vns; oaNativeNS ns; oaScalarName tmpName; oaString tmpNameStr; oaString strOptionValue; try { _args.getLibOption()->getValue(strOptionValue); options.setLibName(strOptionValue); } catch (oaException &err) { const oaString dash("-"); error(dash + _args.getLibOption()->getName() + " \"" + strOptionValue + "\" : " + err.getMsg() + "\n"); return false; } _args.getLibPathOption()->getValue(strOptionValue); options.setLibPath(strOptionValue); _args.getDMSystemOption()->getValue(strOptionValue); options.setDMSystem(strOptionValue); ArgList verilogFiles; verilogOpt.getValue(verilogFiles); for (oaUInt4 i = 0; i < verilogFiles.getNumElements(); i++) { options.addFile(verilogFiles[i]); } if (leafLibsOpt.isSpecified()) { ArgList leafLibs; leafLibsOpt.getValue(leafLibs); options.clearLeafLibs(); for (oaUInt4 i = 0; i < leafLibs.getNumElements(); i++) { try { options.addLeafLib(leafLibs[i]); } catch (oaException &err) { const oaString dash("-"); error(dash + leafLibsOpt.getName() + " \"" + leafLibs[i] + "\" : " + err.getMsg() + "\n"); return false; } } } ArgList leafViews; if (leafViewsOpt.isSpecified()) { leafViewsOpt.getValue(leafViews); } else { leafViews.append("abstract"); } options.clearLeafViews(); for (oaUInt4 i = 0; i < leafViews.getNumElements(); i++) { try { options.addLeafView(leafViews[i]); } catch (oaException &err) { const oaString dash("-"); error(dash + leafViewsOpt.getName() + " \"" + leafViews[i] + "\" : " + err.getMsg() + "\n"); return false; } } if (blackBoxOpt.isSpecified()) { options.enableBlackBox(); } if (designPerModOpt.isSpecified()) { reader.enableDesignPerMod(); } globalsOpt.getValue(strOptionValue); options.setGlobalModuleName(strOptionValue); try { tieHighOpt.getValue(strOptionValue); options.setTieHighNet(oaScalarName(vns, strOptionValue)); } catch (oaException &err) { const oaString dash("-"); error(dash + tieHighOpt.getName() + " \"" + strOptionValue + "\" : " + err.getMsg() + "\n"); return false; } try { tieLowOpt.getValue(strOptionValue); options.setTieLowNet(oaScalarName(vns, strOptionValue)); } catch (oaException &err) { const oaString dash("-"); error(dash + tieLowOpt.getName() + " \"" + strOptionValue + "\" : " + err.getMsg() + "\n"); return false; } if (tolerateOpt.isSpecified()) { options.enableTolerate(); } if (topOpt.getValue(strOptionValue)) { try { options.setTopModuleName(strOptionValue); } catch (oaException &err) { const oaString dash("-"); error(dash + topOpt.getName() + " \"" + strOptionValue + "\" : " + err.getMsg() + "\n"); return false; } } if (_args.getOverwriteOption()->isSpecified()) { options.enableOverwrite(true); } try { viewOpt.getValue(strOptionValue); options.setViewName(strOptionValue); } catch (oaException &err) { const oaString dash("-"); error(dash + viewOpt.getName() + " \"" + strOptionValue + "\" : " + err.getMsg() + "\n"); return false; } viewTypeOpt.getValue(strOptionValue); options.setViewType(strOptionValue); return true;}// *****************************************************************************// oaVerilogInApp::run()//// This function reads the Verilog input according to the given options.// *****************************************************************************voidoaVerilogInApp::run(){ oaVerilogNS vns; oaScalarName libN(options.getLibName()); oaLib *lib = openLib(libN); ArgList leafLibs; if (leafLibsOpt.isSpecified()) { const oaScalarName firstLibName(options.getFirstLeafLib()); oaLib *leafLib = oaLib::find(firstLibName); if (leafLib && oaTech::exists(leafLib)) { oaScalarName leafLibName; oaString leafLibPath; leafLib->getName(leafLibName); leafLib->getPath(leafLibPath); oaTech *tech = LibMgr::getTech(lib, leafLibName, leafLibPath, _libOptions); tech->close(); } else { oaString firstStr; firstLibName.get(vns, firstStr); warning(oaString("Cannot copy tech DB from library \"") + firstStr + "\"\n"); } } reader.getOptions().setLibOptions(_libOptions); reader.parse(); LibMgr::closeAll();}// *****************************************************************************// main()//// This is the main entry point for the Verilog reader application.// *****************************************************************************intmain(int argc, char *argv[]){ try { oaDesignInit(); } catch (oaException &excp) { fprintf(stderr, "ERROR: %s\n", (const char*) excp.getMsg()); exit(1); } oaVerilogInApp app; try { app.main(argc, argv); } catch (oaException &excp) { app.error(excp.getMsg()); } return app.getExitStatus();}
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