82550.txt

用VHDL编写的8250

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ppi IS
 PORT(reset,rd,ws,cs,a0,a1: IN STD_ULOGIC;
       pa:INOUT STD_ULOGIC_VECTOR(7 DOWNTO 0);
       pb:INOUT STD_ULOGIC_VECTOR(7 DOWNTO 0);
       pcl:INOUT STD_ULOGIC_VECTOR(3 DOWENTO 0);
       pch:INOUT STD_ULOGIC_VECTOR(3 DOWNTO 0);
        d:INOUT STD_ULOGIC_VECTOR(7 DOWNTO 0));
END ppi;

ARCHITECTURE rtl OF ppi IS
   SIGNAL internal_bus_out:STD_ULOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL internal_bus_in:STD_ULOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL st,ad,flag:STD_ULOGIC_VECTOR(1 DOWNTO 0);
   SIGNAL ctrreg:STD_ULOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL pa_latch,pb_latch,pc_latch:STD_ULOGIC_VECTOR(7 DOWNTO 0);
  BEGIN
     PROCESS(rd,cs)
        BEGIN 
          st<=ctrreg(3)&ctrreg(0);
          IF(cs='0' AND rd='0')THEN
            IF(a0='0' AND a1='0' AND ctrreg(4)='1')THEN
                internal_bus_in<=(pa);
            ELSIF(a0='1' AND a1='0' AND ctrreg(1)='1')THEN
                internal_bus_in<=pb;
            ELSIF(a0='0' AND a1='1' AND st="01")THEN
                internal_bus_in(3 DOWNTO 0)<=pcl(3 DOWNTO 0);
            ELSIF(a0='0' AND a1='1' AND st="10")THEN
                internal_bus_in(3 DOWNTO 0)<=pch(3 DOWNTO 0);
            ELSIF(a0='0' AND a1='1' AND st="11" AND ctrreg(7)='1')THEN
                internal_bus_in(3 DOWNTO 0)<=pcl(3 DOWNTO 0);
                internal_bus_in(7 DOWNTO 4)<=pch(3 DOWNTO 0);
            END IF;
          ELSE
            internal_bus_in<="ZZZZZZZZ";
          END IF;
          d<=internal_bus_in;
        END PROCESS;


    PROCESS(cs,wr,reset)
       VARIABLE ctrregF:STD_ULOGIC;
       VARIABLE bctrreg_v:STD_ULOGIC_VECTOR(3 DOWNTO 0);
    BEGIN
       IF(cs='0' AND wr='0') THEN
         ad<=a1&a0;
         ctrregF:=d(7);
         internal_bus_out<=d;
       END IF;
       IF(reset='1') THEN
         pa_latch<="00000000";
         pb_latch<="00000000";
         pc_latch<="00000000";
         ctrreg<="10011011";
         bctrreg_v:="0000";
         ctrregF:='0';
       ELSIF(wr'EVENT AND wr='1') THEN
          IF(ctrregF='1' AND ad="11" AND cs='0') THEN
             ctrreg<=internal_bus_out;
          ELSIF(ctrreg(7)='1' AND cs='0' AND ad="00")THEN
             pa_latch<=internal_bus_out;
          ELSIF(ctrreg(7)='1' AND cs='0' AND ad="01")THEN
             pb_latch<=internal_bus_out;
          ELSIF(ctrreg(7)='1' AND cs='0' AND ad="11")THEN
             pc_latch<=internal_bus_out;
          ELSIF(ctrregF='0' AND cs='0' AND ad="11")THEN
             bctrreg_v:=internal_bus_out(3 DOWNTO 0);
             CASE bctrreg_v IS
               WHEN "0000" =>pc_latch(0)<='0';
               WHEN "0010" =>pc_latch(1)<='0';
               WHEN "0100" =>pc_latch(2)<='0';
               WHEN "0110" =>pc_latch(3)<='0';
               WHEN "1000" =>pc_latch(4)<='0';
               WHEN "1010" =>pc_latch(5)<='0';
               WHEN "1100" =>pc_latch(6)<='0';
               WHEN "1110" =>pc_latch(7)<='0';
               WHEN "0001" =>pc_latch(0)<='1';
               WHEN "0011" =>pc_latch(1)<='1';
               WHEN "0101" =>pc_latch(2)<='1';
               WHEN "0111" =>pc_latch(3)<='1';
               WHEN "1001" =>pc_latch(4)<='1';
               WHEN "1011" =>pc_latch(5)<='1';
               WHEN "1101" =>pc_latch(6)<='1';
               WHEN "1111" =>pc_latch(7)<='1';
               WHEN OTHEERS =>flaf<="11";
             END CASE;
          END IF;
         END IF;
     END PROCESS;

 PROCESS(pa_latch)
   BEGIN
     IF(ctrreg(4)='0') THEN
        pa<=(pa_latch);
     ELSE
        pa<="ZZZZZZZZ";
     END IF
   END PROCESS;


PROCESS(pb_latch)
   BEGIN
     IF(ctrreg(1)='0') THEN
        pb<=(pb_latch);
     ELSE
        pb<="ZZZZZZZZ";
     END IF
   END PROCESS;

PROCESS(pc_latch)
   BEGIN
     IF(ctrreg(0)='0') THEN
        pcl<=pc_latch(3 DOWNTO 0);
     ELSE
        pcl<="ZZZZ";
     END IF
   END PROCESS;


PROCESS(pc_latch)
   BEGIN
     IF(ctrreg(3)='0') THEN
        pch<=pc_latch(7 DOWNTO 4);
     ELSE
        pch<="ZZZZ";
     END IF
   END PROCESS;
END rtl;