richic_vga_top.vhm

有关 VHDL进行VGA显示的源程序

      Q => CLK_CNT(10),
      D => CLK_CNT_S(10),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[11]\: FDC port map (
      Q => CLK_CNT(11),
      D => CLK_CNT_S(11),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[12]\: FDC port map (
      Q => CLK_CNT(12),
      D => CLK_CNT_S(12),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[13]\: FDC port map (
      Q => CLK_CNT(13),
      D => CLK_CNT_S(13),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[14]\: FDC port map (
      Q => CLK_CNT(14),
      D => CLK_CNT_S(14),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[15]\: FDC port map (
      Q => CLK_CNT(15),
      D => CLK_CNT_S(15),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[16]\: FDC port map (
      Q => CLK_CNT(16),
      D => CLK_CNT_S(16),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[17]\: FDC port map (
      Q => CLK_CNT(17),
      D => CLK_CNT_S(17),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[18]\: FDC port map (
      Q => CLK_CNT(18),
      D => CLK_CNT_S(18),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[19]\: FDC port map (
      Q => CLK_CNT(19),
      D => CLK_CNT_S(19),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[20]\: FDC port map (
      Q => CLK_CNT(20),
      D => CLK_CNT_S(20),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[21]\: FDC port map (
      Q => CLK_CNT(21),
      D => CLK_CNT_S(21),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[22]\: FDC port map (
      Q => CLK_CNT(22),
      D => CLK_CNT_S(22),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[23]\: FDC port map (
      Q => CLK_CNT(23),
      D => CLK_CNT_S(23),
      C => clk,
      CLR => RST_N_I);
  \II_xpos_i[4]\: INV port map (
      I => XPOS(4),
      O => XPOS_I(4));
  \II_ypos_i[2]\: INV port map (
      I => YPOS(2),
      O => YPOS_I(2));
  II_rst_n_i: INV port map (
      I => rst_n,
      O => RST_N_I);
  II_cursor_wea_i: INV port map (
      I => CURSOR_WEA,
      O => CURSOR_WEA_I);
  II_char_sel_axbxc7: LUT3 
  generic map(
    INIT => X"96"
  )
  port map (
    I0 => CHAR_SEL_P4_0,
    I1 => XPOS_P4_0,
    I2 => X_CNT(9),
    O => CHAR_SEL(9));
  II_word_3: LUT4 
  generic map(
    INIT => X"20A0"
  )
  port map (
    I0 => N_28_2,
    I1 => UN8_WORD0LTO5_2,
    I2 => WORD_3_1,
    I3 => YPOS_E_C2,
    O => WORD_3);
  II_word_3_1: LUT3 
  generic map(
    INIT => X"02"
  )
  port map (
    I0 => YPOS(5),
    I1 => YPOS(6),
    I2 => YPOS(7),
    O => WORD_3_1);
  II_word: LUT3 
  generic map(
    INIT => X"20"
  )
  port map (
    I0 => COLOR,
    I1 => WORD_1_0,
    I2 => WORD_3,
    O => WORD);
  II_word_1_0: LUT4 
  generic map(
    INIT => X"3305"
  )
  port map (
    I0 => UN2_WORD0LT9,
    I1 => UN4_WORD0LT9,
    I2 => XPOS(8),
    I3 => XPOS(9),
    O => WORD_1_0);
  II_N_50_i: LUT4 
  generic map(
    INIT => X"08FF"
  )
  port map (
    I0 => N_52,
    I1 => bg_color(5),
    I2 => PIXEL,
    I3 => VGA_RED0_IV_0,
    O => vga_red0);
  II_N_49_i: LUT4 
  generic map(
    INIT => X"08FF"
  )
  port map (
    I0 => N_52,
    I1 => bg_color(4),
    I2 => PIXEL,
    I3 => VGA_RED1_IV_0,
    O => vga_red1);
  II_vga_red1_iv_0: LUT4_L 
  generic map(
    INIT => X"7F00"
  )
  port map (
    I0 => N_52,
    I1 => fg_color(4),
    I2 => PIXEL,
    I3 => UN2_VGA_RED0_1_I,
    LO => VGA_RED1_IV_0);
  II_vga_red0_iv_0: LUT4_L 
  generic map(
    INIT => X"7F00"
  )
  port map (
    I0 => N_52,
    I1 => fg_color(5),
    I2 => PIXEL,
    I3 => UN2_VGA_RED0_1_I,
    LO => VGA_RED0_IV_0);
  II_vga_green0_0: MUXF5 port map (
      I0 => VGA_GREEN0_0_AM_N,
      I1 => VGA_GREEN0_0_BM_N,
      S => N_52,
      O => vga_green0);
  II_vga_green0_0_bm: LUT3 
  generic map(
    INIT => X"CA"
  )
  port map (
    I0 => bg_color(3),
    I1 => fg_color(3),
    I2 => PIXEL,
    O => VGA_GREEN0_0_BM_N);
  II_vga_green0_0_am: LUT4 
  generic map(
    INIT => X"008C"
  )
  port map (
    I0 => TABLE0,
    I1 => VALID,
    I2 => \VGA_BLUE1_SN.I2_I\,
    I3 => WORD,
    O => VGA_GREEN0_0_AM_N);
  II_vga_green1_0: MUXF5 port map (
      I0 => VGA_GREEN1_0_AM_N,
      I1 => VGA_GREEN1_0_BM_N,
      S => N_52,
      O => vga_green1);
  II_vga_green1_0_bm: LUT3 
  generic map(
    INIT => X"CA"
  )
  port map (
    I0 => bg_color(2),
    I1 => fg_color(2),
    I2 => PIXEL,
    O => VGA_GREEN1_0_BM_N);
  II_vga_green1_0_am: LUT4 
  generic map(
    INIT => X"008C"
  )
  port map (
    I0 => TABLE0,
    I1 => VALID,
    I2 => \VGA_BLUE1_SN.I2_I\,
    I3 => WORD,
    O => VGA_GREEN1_0_AM_N);
  II_vga_blue0_0: MUXF5 port map (
      I0 => VGA_BLUE0_0_AM_N,
      I1 => VGA_BLUE0_0_BM_N,
      S => N_52,
      O => vga_blue0);
  II_vga_blue0_0_bm: LUT3 
  generic map(
    INIT => X"CA"
  )
  port map (
    I0 => bg_color(1),
    I1 => fg_color(1),
    I2 => PIXEL,
    O => VGA_BLUE0_0_BM_N);
  II_vga_blue0_0_am: LUT4 
  generic map(
    INIT => X"008C"
  )
  port map (
    I0 => TABLE0,
    I1 => VALID,
    I2 => \VGA_BLUE1_SN.I2_I\,
    I3 => WORD,
    O => VGA_BLUE0_0_AM_N);
  II_vga_blue1_0: MUXF5 port map (
      I0 => VGA_BLUE1_0_AM_N,
      I1 => VGA_BLUE1_0_BM_N,
      S => N_52,
      O => vga_blue1);
  II_vga_blue1_0_bm: LUT3 
  generic map(
    INIT => X"CA"
  )
  port map (
    I0 => bg_color(0),
    I1 => fg_color(0),
    I2 => PIXEL,
    O => VGA_BLUE1_0_BM_N);
  II_vga_blue1_0_am: LUT2 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => VALID,
    I1 => WORD,
    O => VGA_BLUE1_0_AM_N);
  II_vga_blue1s2: LUT4 
  generic map(
    INIT => X"0080"
  )
  port map (
    I0 => TABLE0,
    I1 => VALID,
    I2 => \VGA_BLUE1_SN.I2_I\,
    I3 => WORD,
    O => N_52);
  II_un2_vga_red0_1: LUT3 
  generic map(
    INIT => X"5D"
  )
  port map (
    I0 => VALID,
    I1 => \VGA_BLUE1_SN.I2_I\,
    I2 => WORD,
    O => UN2_VGA_RED0_1_I);
  II_line0: LUT4 
  generic map(
    INIT => X"00FE"
  )
  port map (
    I0 => N_33,
    I1 => N_45,
    I2 => UN2_LINE0_N,
    I3 => UN14_LINE0_N,
    O => \VGA_BLUE1_SN.I2_I\);
  II_table0: LUT4 
  generic map(
    INIT => X"0001"
  )
  port map (
    I0 => N_28,
    I1 => N_33,
    I2 => N_45,
    I3 => N_48,
    O => TABLE0);
  II_un14_line0: LUT4_L 
  generic map(
    INIT => X"1110"
  )
  port map (
    I0 => N_28,
    I1 => N_48,
    I2 => UN18_LINE0_N,
    I3 => UN21_LINE0_N,
    LO => UN14_LINE0_N);
  II_xpos_e_axbxc3: LUT4 
  generic map(
    INIT => X"01FE"
  )
  port map (
    I0 => XPOS(4),
    I1 => XPOS(5),
    I2 => XPOS(6),
    I3 => XPOS(7),
    O => XPOS_E(7));
  II_un10_table0lto9: LUT4 
  generic map(
    INIT => X"F400"
  )
  port map (
    I0 => UN10_TABLE0LT7,
    I1 => XPOS(7),
    I2 => XPOS(8),
    I3 => XPOS(9),
    O => N_45);
  II_color_15_0: MUXF7 port map (
      I0 => N_19,
      I1 => COLOR_14_0_N,
      S => X_CNT(2),
      O => COLOR);
  II_un18_line0: LUT4 
  generic map(
    INIT => X"0020"
  )
  port map (
    I0 => UN18_LINE0_0,
    I1 => XPOS(6),
    I2 => XPOS(7),
    I3 => XPOS(8),
    O => UN18_LINE0_N);
  II_un8_table0lto9: LUT4 
  generic map(
    INIT => X"000B"
  )
  port map (
    I0 => N_34,
    I1 => XPOS(7),
    I2 => XPOS(8),
    I3 => XPOS(9),
    O => N_33);
  II_color_7_0: MUXF6 port map (
      I0 => COLOR_3_0_N,
      I1 => COLOR_10_0_N,
      S => X_CNT(1),
      O => N_19);
  II_color_14_0: MUXF6 port map (
      I0 => COLOR_6_0_N,
      I1 => COLOR_13_0_N,
      S => X_CNT(1),
      O => COLOR_14_0_N);
  II_un18_line0_0: LUT4_L 
  generic map(
    INIT => X"0008"
  )
  port map (
    I0 => UN18_LINE0_6,
    I1 => XPOS(4),
    I2 => XPOS(5),
    I3 => XPOS(9),
    LO => UN18_LINE0_0);
  II_un4_word0lto8: LUT4 
  generic map(
    INIT => X"000B"
  )
  port map (
    I0 => UN4_WORD0LT6,
    I1 => XPOS(6),
    I2 => XPOS(7),
    I3 => XPOS(8),
    O => UN4_WORD0LT9);
  II_un21_line0: LUT4 
  generic map(
    INIT => X"0200"
  )
  port map (
    I0 => UN21_LINE0_6,
    I1 => XPOS(5),
    I2 => XPOS(8),
    I3 => XPOS(9),
    O => UN21_LINE0_N);
  II_xpos_e_axbxc2: LUT3 
  generic map(
    INIT => X"E1"
  )
  port map (
    I0 => XPOS(4),
    I1 => XPOS(5),
    I2 => XPOS(6),
    O => XPOS_E(6));
  II_N_398_i: LUT2 
  generic map(
    INIT => X"E"
  )
  port map (
    I0 => DINA_I_O3_I_A2_N(1),
    I1 => ascii_in(2),
    O => N_398_I);
  II_wea_i_m3_i_m2_i_m2_i_m2: LUT3 
  generic map(
    INIT => X"E4"
  )
  port map (
    I0 => DINA_I_O3_I_A2_N(1),
    I1 => ascii_wea,
    I2 => CURSOR_WEA,
    O => WEA_I_M3_I_M2_I_M2_I_M2_N);
  \II_dina_i_m3_i_m2_i_m2_i_m2[0]\: LUT3 
  generic map(
    INIT => X"4E"
  )
  port map (
    I0 => DINA_I_O3_I_A2_N(1),
    I1 => ascii_in(0),
    I2 => CLK_CNT(23),
    O => DINA_I_M3_I_M2_I_M2_I_M2_N(0));
  II_un21_line0_6: LUT4 
  generic map(
    INIT => X"0800"
  )
  port map (
    I0 => UN21_LINE0_2,
    I1 => XPOS(4),
    I2 => XPOS(6),
    I3 => XPOS(7),
    O => UN21_LINE0_6);
  II_un2_word0lto7: LUT4 
  generic map(
    INIT => X"D000"
  )
  port map (
    I0 => UN2_WORD0LTO5_0,
    I1 => XPOS(5),
    I2 => XPOS(6),
    I3 => XPOS(7),
    O => UN2_WORD0LT9);
  II_un8_table0lto6: LUT4 
  generic map(
    INIT => X"000B"
  )
  port map (
    I0 => UN18_LINE0_6,
    I1 => XPOS(4),
    I2 => XPOS(5),
    I3 => XPOS(6),
    O => N_34);
  II_un10_table0lto6: LUT4 
  generic map(
    INIT => X"000B"
  )
  port map (
    I0 => UN10_TABLE0LT4,
    I1 => XPOS(4),
    I2 => XPOS(5),
    I3 => XPOS(6),
    O => UN10_TABLE0LT7);
  II_color_6_0: MUXF5 port map (
      I0 => COLOR_6_0_AM_N,
      I1 => COLOR_6_0_BM_N,
      S => X_CNT(4),
      O => COLOR_6_0_N);
  II_color_6_0_bm: LUT4 
  generic map(
    INIT => X"0A0C"
  )
  port map (
    I0 => N_505_I,
    I1 => N_509_I,
    I2 => CHAR_SEL(9),
    I3 => X_CNT(3),
    O => COLOR_6_0_BM_N);
  II_color_6_0_am: LUT4 
  generic map(
    INIT => X"0A0C"
  )
  port map (
    I0 => N_513_I,
    I1 => N_517_I,
    I2 => CHAR_SEL(9),
    I3 => X_CNT(3),
    O => COLOR_6_0_AM_N);
  II_color_3_0: MUXF5 port map (
      I0 => COLOR_3_0_AM_N,
      I1 => COLOR_3_0_BM_N,
      S => X_CNT(4),
      O => COLOR_3_0_N);
  II_color_3_0_bm: LUT4 
  generic map(
    INIT => X"0A0C"
  )
  port map (
    I0 => N_507_I,
    I1 => N_511_I,
    I2 => CHAR_SEL(9),
    I3 => X_CNT(3),
    O => COLOR_3_0_BM_N);
  II_color_3_0_am: LUT4 
  generic map(
    INIT => X"0C0A"
  )
  port map (
    I0 => N_504_I,
    I1 => N_515_I,
    I2 => CHAR_SEL(9),
    I3 => X_CNT(3),
    O => COLOR_3_0_AM_N);
  II_color_10_0: MUXF5 port map (
      I0 => COLOR_10_0_AM_N,
      I1 => COLOR_10_0_BM_N,
      S => X_CNT(3),
      O => COLOR_10_0_N);
  II_color_10_0_bm: LUT4 
  generic map(
    INIT => X"0A0C"
  )
  port map (
    I0 => N_506_I,
    I1 => N_514_I,
    I2 => CHAR_SEL(9),
    I3 => X_CNT(4),
    O => COLOR_10_0_BM_N);
  II_color_10_0_am: LUT4 
  generic map(
    INIT => X"0A0C"
  )
  port map (
    I0 => N_510_I,
    I1 => N_518_I,
    I2 => CHAR_SEL(9),
    I3 => X_CNT(4),
    O => COLOR_10_0_AM_N);
  II_cursor_wea7_0_a3_0_a2_0_a2_0_a2: