richic_vga_top.vhm

有关 VHDL进行VGA显示的源程序

  signal XPOS_E : std_logic_vector (8 downto 5);
  signal DINA_I_O3_I_A2_N : std_logic_vector (1 to 1);
  signal DINA_I_M3_I_M2_I_M2_I_M2_N : std_logic_vector (0 to 0);
  signal DINA_I_I_A2_0_A2_0_A2_N : std_logic_vector (7 downto 1);
  signal DINA_I_O3_I_A2_13 : std_logic_vector (1 to 1);
  signal DINA_I_O3_I_A2_14 : std_logic_vector (1 to 1);
  signal DINA_I_O3_I_A2_17 : std_logic_vector (1 to 1);
  signal DINA_I_O3_I_A2_19 : std_logic_vector (1 to 1);
  signal YPOS_E : std_logic_vector (8 downto 3);
  signal DINA_I_O3_I_A2_12 : std_logic_vector (1 to 1);
  signal DINA_I_O3_I_A2_3 : std_logic_vector (1 to 1);
  signal DINA_I_O3_I_A2_16 : std_logic_vector (1 to 1);
  signal CHAR_E : std_logic_vector (7 downto 0);
  signal CLK_CNT_CRY : std_logic_vector (22 downto 0);
  signal ADDRA : std_logic_vector (9 downto 0);
  signal Y_CNT_I : std_logic_vector (0 to 0);
  signal ASCII : std_logic_vector (7 downto 0);
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal YPOS_AXB_1 : std_logic ;
  signal YPOS_S_2_SF : std_logic ;
  signal YPOS_S_3_SF : std_logic ;
  signal YPOS_S_4_SF : std_logic ;
  signal YPOS_AXB_5 : std_logic ;
  signal YPOS_S_6_SF : std_logic ;
  signal YPOS_S_7_SF : std_logic ;
  signal YPOS_S_8_SF : std_logic ;
  signal ADDRA_AXB_0 : std_logic ;
  signal ADDRA_AXB_1 : std_logic ;
  signal ADDRA_AXB_2 : std_logic ;
  signal ADDRA_AXB_3 : std_logic ;
  signal ADDRA_AXB_4 : std_logic ;
  signal ADDRA_AXB_5 : std_logic ;
  signal ADDRA_AXB_6 : std_logic ;
  signal ADDRA_AXB_7 : std_logic ;
  signal ADDRA_AXB_8 : std_logic ;
  signal CURSOR_WEA : std_logic ;
  signal CURSOR_WEA_I : std_logic ;
  signal RST_N_I : std_logic ;
  signal CURSOR_WEA7 : std_logic ;
  signal CHAR_SEL_P4_0 : std_logic ;
  signal XPOS_P4_0 : std_logic ;
  signal N_28_2 : std_logic ;
  signal UN8_WORD0LTO5_2 : std_logic ;
  signal WORD_3_1 : std_logic ;
  signal YPOS_E_C2 : std_logic ;
  signal WORD_3 : std_logic ;
  signal COLOR : std_logic ;
  signal WORD_1_0 : std_logic ;
  signal WORD : std_logic ;
  signal UN2_WORD0LT9 : std_logic ;
  signal UN4_WORD0LT9 : std_logic ;
  signal N_52 : std_logic ;
  signal PIXEL : std_logic ;
  signal VGA_RED0_IV_0 : std_logic ;
  signal VGA_RED1_IV_0 : std_logic ;
  signal UN2_VGA_RED0_1_I : std_logic ;
  signal VGA_GREEN0_0_AM_N : std_logic ;
  signal VGA_GREEN0_0_BM_N : std_logic ;
  signal TABLE0 : std_logic ;
  signal VALID : std_logic ;
  signal \VGA_BLUE1_SN.I2_I\ : std_logic ;
  signal VGA_GREEN1_0_AM_N : std_logic ;
  signal VGA_GREEN1_0_BM_N : std_logic ;
  signal VGA_BLUE0_0_AM_N : std_logic ;
  signal VGA_BLUE0_0_BM_N : std_logic ;
  signal VGA_BLUE1_0_AM_N : std_logic ;
  signal VGA_BLUE1_0_BM_N : std_logic ;
  signal N_33 : std_logic ;
  signal N_45 : std_logic ;
  signal UN2_LINE0_N : std_logic ;
  signal UN14_LINE0_N : std_logic ;
  signal N_28 : std_logic ;
  signal N_48 : std_logic ;
  signal UN18_LINE0_N : std_logic ;
  signal UN21_LINE0_N : std_logic ;
  signal UN10_TABLE0LT7 : std_logic ;
  signal N_19 : std_logic ;
  signal COLOR_14_0_N : std_logic ;
  signal UN18_LINE0_0 : std_logic ;
  signal N_34 : std_logic ;
  signal COLOR_3_0_N : std_logic ;
  signal COLOR_10_0_N : std_logic ;
  signal COLOR_6_0_N : std_logic ;
  signal COLOR_13_0_N : std_logic ;
  signal UN18_LINE0_6 : std_logic ;
  signal UN4_WORD0LT6 : std_logic ;
  signal UN21_LINE0_6 : std_logic ;
  signal N_398_I : std_logic ;
  signal WEA_I_M3_I_M2_I_M2_I_M2_N : std_logic ;
  signal UN21_LINE0_2 : std_logic ;
  signal UN2_WORD0LTO5_0 : std_logic ;
  signal UN10_TABLE0LT4 : std_logic ;
  signal COLOR_6_0_AM_N : std_logic ;
  signal COLOR_6_0_BM_N : std_logic ;
  signal N_505_I : std_logic ;
  signal N_509_I : std_logic ;
  signal N_513_I : std_logic ;
  signal N_517_I : std_logic ;
  signal COLOR_3_0_AM_N : std_logic ;
  signal COLOR_3_0_BM_N : std_logic ;
  signal N_507_I : std_logic ;
  signal N_511_I : std_logic ;
  signal N_504_I : std_logic ;
  signal N_515_I : std_logic ;
  signal COLOR_10_0_AM_N : std_logic ;
  signal COLOR_10_0_BM_N : std_logic ;
  signal N_506_I : std_logic ;
  signal N_514_I : std_logic ;
  signal N_510_I : std_logic ;
  signal N_518_I : std_logic ;
  signal COLOR_13_0_AM_N : std_logic ;
  signal COLOR_13_0_BM_N : std_logic ;
  signal N_512_I : std_logic ;
  signal N_508_I : std_logic ;
  signal N_516_I : std_logic ;
  signal N_29 : std_logic ;
  signal CHAR_SEL_P4 : std_logic ;
  signal XPOS_E_P4 : std_logic ;
  signal N_47 : std_logic ;
  signal UN5_LINE0_2 : std_logic ;
  signal UN5_LINE0_3 : std_logic ;
  signal UN8_LINE0_N : std_logic ;
  signal N_303 : std_logic ;
  signal N_306 : std_logic ;
  signal N_35_2 : std_logic ;
  signal UN8_LINE0_3 : std_logic ;
  signal UN8_LINE0_4 : std_logic ;
  signal YPOS_E_P4 : std_logic ;
  signal XPOS_P4 : std_logic ;
  signal UN8_LINE0_2 : std_logic ;
  signal PIXEL_3_0_AM_N : std_logic ;
  signal PIXEL_3_0_BM_N : std_logic ;
  signal PIXEL_6_0_AM_N : std_logic ;
  signal PIXEL_6_0_BM_N : std_logic ;
  signal YPOS_S_9_SF : std_logic ;
  signal ADDRA_AXB_9 : std_logic ;
  signal ADDRA_CRY_8 : std_logic ;
  signal ADDRA_CRY_7 : std_logic ;
  signal ADDRA_CRY_6 : std_logic ;
  signal ADDRA_CRY_5 : std_logic ;
  signal ADDRA_CRY_4 : std_logic ;
  signal ADDRA_CRY_3 : std_logic ;
  signal ADDRA_CRY_2 : std_logic ;
  signal ADDRA_CRY_1 : std_logic ;
  signal ADDRA_CRY_0 : std_logic ;
  signal YPOS_CRY_8 : std_logic ;
  signal YPOS_CRY_7 : std_logic ;
  signal YPOS_CRY_6 : std_logic ;
  signal YPOS_CRY_5 : std_logic ;
  signal YPOS_CRY_4 : std_logic ;
  signal YPOS_CRY_3 : std_logic ;
  signal YPOS_CRY_2 : std_logic ;
  signal YPOS_CRY_1 : std_logic ;
  signal YPOS_CRY_0 : std_logic ;
  component rom2048x8
    port(
      addr : in std_logic_vector (10 downto 0);
      clk : in std_logic;
      dout : out std_logic_vector (7 downto 0)  );
  end component;
  component ram1024x8
    port(
      addra : in std_logic_vector (9 downto 0);
      addrb : in std_logic_vector (9 downto 0);
      clka : in std_logic;
      clkb : in std_logic;
      dina : in std_logic_vector (7 downto 0);
      doutb : out std_logic_vector (7 downto 0);
      wea : in std_logic  );
  end component;
  component sync_gen_50m_1
    port(
      y_cnt_i : out std_logic_vector (0 downto 0);
      y_cnt : out std_logic_vector (9 downto 0);
      x_cnt : out std_logic_vector (9 downto 0);
      N_35_2 : out std_logic;
      valid : out std_logic;
      vga_vsync : out std_logic;
      vga_hsync : out std_logic;
      rst_n_i : in std_logic;
      clk : in std_logic  );
  end component;
  component char_rom_rhic_1
    port(
      char_sel : in std_logic_vector (8 downto 7);
      ypos : in std_logic_vector (4 downto 1);
      x_cnt : in std_logic_vector (6 downto 5);
      N_505_i : out std_logic;
      N_506_i : out std_logic;
      N_507_i : out std_logic;
      N_508_i : out std_logic;
      N_509_i : out std_logic;
      N_510_i : out std_logic;
      N_511_i : out std_logic;
      N_512_i : out std_logic;
      N_513_i : out std_logic;
      N_514_i : out std_logic;
      N_515_i : out std_logic;
      N_516_i : out std_logic;
      N_517_i : out std_logic;
      N_518_i : out std_logic;
      N_504_i : out std_logic  );
  end component;
begin
  II_ypos_axb_1: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => Y_CNT(1),
    O => YPOS_AXB_1);
  II_ypos_s_2_sf: LUT1 
  generic map(
    INIT => X"1"
  )
  port map (
    I0 => Y_CNT(2),
    O => YPOS_S_2_SF);
  II_ypos_s_3_sf: LUT1 
  generic map(
    INIT => X"1"
  )
  port map (
    I0 => Y_CNT(3),
    O => YPOS_S_3_SF);
  II_ypos_s_4_sf: LUT1 
  generic map(
    INIT => X"1"
  )
  port map (
    I0 => Y_CNT(4),
    O => YPOS_S_4_SF);
  II_ypos_axb_5: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => Y_CNT(5),
    O => YPOS_AXB_5);
  II_ypos_s_6_sf: LUT1 
  generic map(
    INIT => X"1"
  )
  port map (
    I0 => Y_CNT(6),
    O => YPOS_S_6_SF);
  II_ypos_s_7_sf: LUT1 
  generic map(
    INIT => X"1"
  )
  port map (
    I0 => Y_CNT(7),
    O => YPOS_S_7_SF);
  II_ypos_s_8_sf: LUT1 
  generic map(
    INIT => X"1"
  )
  port map (
    I0 => Y_CNT(8),
    O => YPOS_S_8_SF);
  II_addra_axb_0: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => word_num(0),
    O => ADDRA_AXB_0);
  II_addra_axb_1: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => word_num(1),
    O => ADDRA_AXB_1);
  II_addra_axb_2: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => word_num(2),
    O => ADDRA_AXB_2);
  II_addra_axb_3: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => word_num(3),
    O => ADDRA_AXB_3);
  II_addra_axb_4: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => word_num(4),
    O => ADDRA_AXB_4);
  II_addra_axb_5: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => line_num(0),
    O => ADDRA_AXB_5);
  II_addra_axb_6: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => line_num(1),
    O => ADDRA_AXB_6);
  II_addra_axb_7: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => line_num(2),
    O => ADDRA_AXB_7);
  II_addra_axb_8: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => line_num(3),
    O => ADDRA_AXB_8);
  \II_clk_cnt_qxu_0[0]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(0),
    O => CLK_CNT_QXU(0));
  \II_clk_cnt_qxu_0[1]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(1),
    O => CLK_CNT_QXU(1));
  \II_clk_cnt_qxu_0[2]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(2),
    O => CLK_CNT_QXU(2));
  \II_clk_cnt_qxu_0[3]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(3),
    O => CLK_CNT_QXU(3));
  \II_clk_cnt_qxu_0[4]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(4),
    O => CLK_CNT_QXU(4));
  \II_clk_cnt_qxu_0[5]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(5),
    O => CLK_CNT_QXU(5));
  \II_clk_cnt_qxu_0[6]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(6),
    O => CLK_CNT_QXU(6));
  \II_clk_cnt_qxu_0[7]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(7),
    O => CLK_CNT_QXU(7));
  \II_clk_cnt_qxu_0[8]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(8),
    O => CLK_CNT_QXU(8));
  \II_clk_cnt_qxu_0[9]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(9),
    O => CLK_CNT_QXU(9));
  \II_clk_cnt_qxu_0[10]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(10),
    O => CLK_CNT_QXU(10));
  \II_clk_cnt_qxu_0[11]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(11),
    O => CLK_CNT_QXU(11));
  \II_clk_cnt_qxu_0[12]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(12),
    O => CLK_CNT_QXU(12));
  \II_clk_cnt_qxu_0[13]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(13),
    O => CLK_CNT_QXU(13));
  \II_clk_cnt_qxu_0[14]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(14),
    O => CLK_CNT_QXU(14));
  \II_clk_cnt_qxu_0[15]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(15),
    O => CLK_CNT_QXU(15));
  \II_clk_cnt_qxu_0[16]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(16),
    O => CLK_CNT_QXU(16));
  \II_clk_cnt_qxu_0[17]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(17),
    O => CLK_CNT_QXU(17));
  \II_clk_cnt_qxu_0[18]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(18),
    O => CLK_CNT_QXU(18));
  \II_clk_cnt_qxu_0[19]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(19),
    O => CLK_CNT_QXU(19));
  \II_clk_cnt_qxu_0[20]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(20),
    O => CLK_CNT_QXU(20));
  \II_clk_cnt_qxu_0[21]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(21),
    O => CLK_CNT_QXU(21));
  \II_clk_cnt_qxu_0[22]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(22),
    O => CLK_CNT_QXU(22));
  \II_clk_cnt_qxu_0[23]\: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => CLK_CNT(23),
    O => CLK_CNT_QXU(23));
  II_cursor_wea: FDPE port map (
      Q => CURSOR_WEA,
      D => CURSOR_WEA_I,
      C => clk,
      PRE => RST_N_I,
      CE => CURSOR_WEA7);
  \II_clk_cnt[0]\: FDC port map (
      Q => CLK_CNT(0),
      D => CLK_CNT_S(0),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[1]\: FDC port map (
      Q => CLK_CNT(1),
      D => CLK_CNT_S(1),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[2]\: FDC port map (
      Q => CLK_CNT(2),
      D => CLK_CNT_S(2),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[3]\: FDC port map (
      Q => CLK_CNT(3),
      D => CLK_CNT_S(3),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[4]\: FDC port map (
      Q => CLK_CNT(4),
      D => CLK_CNT_S(4),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[5]\: FDC port map (
      Q => CLK_CNT(5),
      D => CLK_CNT_S(5),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[6]\: FDC port map (
      Q => CLK_CNT(6),
      D => CLK_CNT_S(6),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[7]\: FDC port map (
      Q => CLK_CNT(7),
      D => CLK_CNT_S(7),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[8]\: FDC port map (
      Q => CLK_CNT(8),
      D => CLK_CNT_S(8),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[9]\: FDC port map (
      Q => CLK_CNT(9),
      D => CLK_CNT_S(9),
      C => clk,
      CLR => RST_N_I);
  \II_clk_cnt[10]\: FDC port map (