richic_vga_top.vhm

有关 VHDL进行VGA显示的源程序

  II_data_1130_5: ROM64X1 
  generic map(
    INIT => X"03111377B15359F4"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    O => DATA_1130_5);
  II_data_10_5: ROM128X1 
  generic map(
    INIT => X"000000000000000000208481089BBBBB"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    A6 => char_sel(7),
    O => DATA_10_5);
  II_data_1130_4: ROM64X1 
  generic map(
    INIT => X"0828C88CC01221A4"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    O => DATA_1130_4);
  II_data_19_4: ROM128X1 
  generic map(
    INIT => X"0000000000000000032B3D1120918020"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    A6 => char_sel(7),
    O => DATA_19_4);
  II_data_1130_3: ROM64X1 
  generic map(
    INIT => X"20A4040488120184"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    O => DATA_1130_3);
  II_data_12_3: ROM128X1 
  generic map(
    INIT => X"00000000000000004E54444FC4D5C464"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    A6 => char_sel(7),
    O => DATA_12_3);
  II_data_1130_2: ROM64X1 
  generic map(
    INIT => X"04E0040880920184"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    O => DATA_1130_2);
  II_data_14_2: ROM128X1 
  generic map(
    INIT => X"00000000000000001880222500919130"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    A6 => char_sel(7),
    O => DATA_14_2);
  II_data_1132_1: ROM64X1 
  generic map(
    INIT => X"0888000080120180"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    O => DATA_1132_1);
  II_data_19_1: ROM128X1 
  generic map(
    INIT => X"00000000000000000911113500108020"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    A6 => char_sel(7),
    O => DATA_19_1);
  II_GND: GND port map (
      G => NN_1);
  II_VCC: VCC port map (
      P => NN_2);
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity sync_gen_50m_1 is
port(
  y_cnt_i : out std_logic_vector (0 downto 0);
  y_cnt : out std_logic_vector (9 downto 0);
  x_cnt : out std_logic_vector (9 downto 0);
  N_35_2 :  out std_logic;
  valid :  out std_logic;
  vga_vsync :  out std_logic;
  vga_hsync :  out std_logic;
  rst_n_i :  in std_logic;
  clk :  in std_logic);
end sync_gen_50m_1;

architecture beh of sync_gen_50m_1 is
  signal X_CNT_6 : std_logic_vector (9 downto 0);
  signal Y_CNT_6 : std_logic_vector (9 downto 0);
  signal Y_CNT_0_INT_1 : std_logic ;
  signal Y_CNT_1_INT_2 : std_logic ;
  signal Y_CNT_2_INT_3 : std_logic ;
  signal Y_CNT_3_INT_4 : std_logic ;
  signal Y_CNT_4_INT_5 : std_logic ;
  signal Y_CNT_5_INT_6 : std_logic ;
  signal Y_CNT_6_INT_7 : std_logic ;
  signal Y_CNT_7_INT_8 : std_logic ;
  signal Y_CNT_8_INT_9 : std_logic ;
  signal Y_CNT_9_INT_10 : std_logic ;
  signal X_CNT_0_INT_11 : std_logic ;
  signal X_CNT_1_INT_12 : std_logic ;
  signal X_CNT_2_INT_13 : std_logic ;
  signal X_CNT_3_INT_14 : std_logic ;
  signal X_CNT_4_INT_15 : std_logic ;
  signal X_CNT_5_INT_16 : std_logic ;
  signal X_CNT_6_INT_17 : std_logic ;
  signal X_CNT_7_INT_18 : std_logic ;
  signal X_CNT_8_INT_19 : std_logic ;
  signal X_CNT_9_INT_20 : std_logic ;
  signal N_35_2_INT_21 : std_logic ;
  signal UN6_X_CNT_AXB_0 : std_logic ;
  signal UN6_X_CNT_AXB_1 : std_logic ;
  signal UN6_X_CNT_AXB_2 : std_logic ;
  signal UN6_X_CNT_AXB_3 : std_logic ;
  signal UN6_X_CNT_AXB_4 : std_logic ;
  signal UN6_X_CNT_AXB_5 : std_logic ;
  signal UN6_X_CNT_AXB_6 : std_logic ;
  signal UN6_X_CNT_AXB_7 : std_logic ;
  signal UN6_X_CNT_AXB_8 : std_logic ;
  signal UN1_Y_CNT_1_AXB_0 : std_logic ;
  signal UN1_Y_CNT_1_AXB_1 : std_logic ;
  signal UN1_Y_CNT_1_AXB_2 : std_logic ;
  signal UN1_Y_CNT_1_AXB_3 : std_logic ;
  signal UN1_Y_CNT_1_AXB_4 : std_logic ;
  signal UN1_Y_CNT_1_AXB_5 : std_logic ;
  signal UN1_Y_CNT_1_AXB_6 : std_logic ;
  signal UN1_Y_CNT_1_AXB_7 : std_logic ;
  signal UN1_Y_CNT_1_AXB_8 : std_logic ;
  signal VALID_3_138_N : std_logic ;
  signal UN5_VALIDLTO9_N : std_logic ;
  signal UN7_VALIDLT9 : std_logic ;
  signal UN7_VALIDLTO9_1 : std_logic ;
  signal VALID_3 : std_logic ;
  signal UN5_VSYNCLTO9_4 : std_logic ;
  signal UN5_VSYNCLTO9_N : std_logic ;
  signal UN5_HSYNCLTO3_N : std_logic ;
  signal UN5_HSYNCLTO9_1 : std_logic ;
  signal UN5_HSYNCLTO9_N : std_logic ;
  signal UN6_X_CNT_S_6_N : std_logic ;
  signal X_CNT14 : std_logic ;
  signal UN6_X_CNT_S_5_N : std_logic ;
  signal UN6_X_CNT_S_3_N : std_logic ;
  signal UN1_Y_CNT_1_S_9_N : std_logic ;
  signal Y_CNT14 : std_logic ;
  signal UN1_Y_CNT_1_S_7_N : std_logic ;
  signal UN1_Y_CNT_1_S_4_N : std_logic ;
  signal UN1_Y_CNT_1_S_3_N : std_logic ;
  signal UN1_Y_CNT_1_S_0_N : std_logic ;
  signal UN6_X_CNT_S_9_N : std_logic ;
  signal UN6_X_CNT_S_8_N : std_logic ;
  signal UN6_X_CNT_S_7_N : std_logic ;
  signal UN1_Y_CNT_1_S_1_N : std_logic ;
  signal UN1_Y_CNT_1_S_2_N : std_logic ;
  signal UN1_Y_CNT_1_S_5_N : std_logic ;
  signal UN1_Y_CNT_1_S_6_N : std_logic ;
  signal UN1_Y_CNT_1_S_8_N : std_logic ;
  signal UN6_X_CNT_S_1_N : std_logic ;
  signal UN6_X_CNT_S_2_N : std_logic ;
  signal UN6_X_CNT_S_4_N : std_logic ;
  signal UN5_VALIDLTO6_N : std_logic ;
  signal UN9_VALIDLTO9_N : std_logic ;
  signal UN11_VALIDLTO6_N : std_logic ;
  signal UN9_VALIDLTO9_1 : std_logic ;
  signal UN5_VALIDLTO3_N : std_logic ;
  signal X_CNT14_3 : std_logic ;
  signal X_CNT14_4 : std_logic ;
  signal Y_CNT14_4 : std_logic ;
  signal Y_CNT14_5 : std_logic ;
  signal UN9_VALIDLT9 : std_logic ;
  signal UN5_VSYNCLTO9_3 : std_logic ;
  signal UN11_VALIDLTO6_2 : std_logic ;
  signal UN1_Y_CNT_1_AXB_9 : std_logic ;
  signal UN6_X_CNT_AXB_9 : std_logic ;
  signal UN1_Y_CNT_1_CRY_8 : std_logic ;
  signal UN1_Y_CNT_1_CRY_7 : std_logic ;
  signal NN_1 : std_logic ;
  signal UN1_Y_CNT_1_CRY_6 : std_logic ;
  signal UN1_Y_CNT_1_CRY_5 : std_logic ;
  signal UN1_Y_CNT_1_CRY_4 : std_logic ;
  signal UN1_Y_CNT_1_CRY_3 : std_logic ;
  signal UN1_Y_CNT_1_CRY_2 : std_logic ;
  signal UN1_Y_CNT_1_CRY_1 : std_logic ;
  signal UN1_Y_CNT_1_CRY_0 : std_logic ;
  signal UN6_X_CNT_CRY_8 : std_logic ;
  signal UN6_X_CNT_CRY_7 : std_logic ;
  signal UN6_X_CNT_CRY_6 : std_logic ;
  signal UN6_X_CNT_CRY_5 : std_logic ;
  signal UN6_X_CNT_CRY_4 : std_logic ;
  signal UN6_X_CNT_CRY_3 : std_logic ;
  signal UN6_X_CNT_CRY_2 : std_logic ;
  signal UN6_X_CNT_CRY_1 : std_logic ;
  signal UN6_X_CNT_CRY_0 : std_logic ;
  signal NN_2 : std_logic ;
begin
  II_un6_x_cnt_axb_0: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => X_CNT_0_INT_11,
    O => UN6_X_CNT_AXB_0);
  II_un6_x_cnt_axb_1: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => X_CNT_1_INT_12,
    O => UN6_X_CNT_AXB_1);
  II_un6_x_cnt_axb_2: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => X_CNT_2_INT_13,
    O => UN6_X_CNT_AXB_2);
  II_un6_x_cnt_axb_3: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => X_CNT_3_INT_14,
    O => UN6_X_CNT_AXB_3);
  II_un6_x_cnt_axb_4: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => X_CNT_4_INT_15,
    O => UN6_X_CNT_AXB_4);
  II_un6_x_cnt_axb_5: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => X_CNT_5_INT_16,
    O => UN6_X_CNT_AXB_5);
  II_un6_x_cnt_axb_6: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => X_CNT_6_INT_17,
    O => UN6_X_CNT_AXB_6);
  II_un6_x_cnt_axb_7: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => X_CNT_7_INT_18,
    O => UN6_X_CNT_AXB_7);
  II_un6_x_cnt_axb_8: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => X_CNT_8_INT_19,
    O => UN6_X_CNT_AXB_8);
  II_un1_y_cnt_1_axb_0: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => Y_CNT_0_INT_1,
    O => UN1_Y_CNT_1_AXB_0);
  II_un1_y_cnt_1_axb_1: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => Y_CNT_1_INT_2,
    O => UN1_Y_CNT_1_AXB_1);
  II_un1_y_cnt_1_axb_2: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => Y_CNT_2_INT_3,
    O => UN1_Y_CNT_1_AXB_2);
  II_un1_y_cnt_1_axb_3: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => Y_CNT_3_INT_4,
    O => UN1_Y_CNT_1_AXB_3);
  II_un1_y_cnt_1_axb_4: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => Y_CNT_4_INT_5,
    O => UN1_Y_CNT_1_AXB_4);
  II_un1_y_cnt_1_axb_5: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => Y_CNT_5_INT_6,
    O => UN1_Y_CNT_1_AXB_5);
  II_un1_y_cnt_1_axb_6: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => Y_CNT_6_INT_7,
    O => UN1_Y_CNT_1_AXB_6);
  II_un1_y_cnt_1_axb_7: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => Y_CNT_7_INT_8,
    O => UN1_Y_CNT_1_AXB_7);
  II_un1_y_cnt_1_axb_8: LUT1 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => Y_CNT_8_INT_9,
    O => UN1_Y_CNT_1_AXB_8);
  II_valid_3: LUT4_L 
  generic map(
    INIT => X"2022"
  )
  port map (
    I0 => VALID_3_138_N,
    I1 => UN5_VALIDLTO9_N,
    I2 => UN7_VALIDLT9,
    I3 => UN7_VALIDLTO9_1,
    LO => VALID_3);
  II_un5_vsynclto9: LUT4_L 
  generic map(
    INIT => X"2AAA"
  )
  port map (
    I0 => UN5_VSYNCLTO9_4,
    I1 => Y_CNT_0_INT_1,
    I2 => Y_CNT_1_INT_2,
    I3 => Y_CNT_2_INT_3,
    LO => UN5_VSYNCLTO9_N);
  II_un5_hsynclto9: LUT4_L 
  generic map(
    INIT => X"8CCC"
  )
  port map (
    I0 => UN5_HSYNCLTO3_N,
    I1 => UN5_HSYNCLTO9_1,
    I2 => X_CNT_4_INT_15,
    I3 => X_CNT_5_INT_16,
    LO => UN5_HSYNCLTO9_N);
  \II_x_cnt_6[6]\: LUT2_L 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => UN6_X_CNT_S_6_N,
    I1 => X_CNT14,
    LO => X_CNT_6(6));
  \II_x_cnt_6[5]\: LUT2_L 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => UN6_X_CNT_S_5_N,
    I1 => X_CNT14,
    LO => X_CNT_6(5));
  \II_x_cnt_6[3]\: LUT2_L 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => UN6_X_CNT_S_3_N,
    I1 => X_CNT14,
    LO => X_CNT_6(3));
  \II_x_cnt_6[0]\: LUT2_L 
  generic map(
    INIT => X"1"
  )
  port map (
    I0 => X_CNT14,
    I1 => X_CNT_0_INT_11,
    LO => X_CNT_6(0));
  \II_y_cnt_6[9]\: LUT2_L 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => UN1_Y_CNT_1_S_9_N,
    I1 => Y_CNT14,
    LO => Y_CNT_6(9));
  \II_y_cnt_6[7]\: LUT2_L 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => UN1_Y_CNT_1_S_7_N,
    I1 => Y_CNT14,
    LO => Y_CNT_6(7));
  \II_y_cnt_6[4]\: LUT2_L 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => UN1_Y_CNT_1_S_4_N,
    I1 => Y_CNT14,
    LO => Y_CNT_6(4));
  \II_y_cnt_6[3]\: LUT2_L 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => UN1_Y_CNT_1_S_3_N,
    I1 => Y_CNT14,
    LO => Y_CNT_6(3));
  \II_y_cnt_6[0]\: LUT2_L 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => UN1_Y_CNT_1_S_0_N,
    I1 => Y_CNT14,
    LO => Y_CNT_6(0));
  \II_x_cnt_6[9]\: LUT2_L 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => UN6_X_CNT_S_9_N,
    I1 => X_CNT14,
    LO => X_CNT_6(9));
  \II_x_cnt_6[8]\: LUT2_L 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => UN6_X_CNT_S_8_N,
    I1 => X_CNT14,
    LO => X_CNT_6(8));
  \II_x_cnt_6[7]\: LUT2_L 
  generic map(
    INIT => X"2"
  )
  port map (
    I0 => UN6_X_CNT_S_7_N,
    I1 => X_CNT14,
    LO => X_CNT_6(7));
  \II_x_cnt[7]\: FDC port map (
      Q => X_CNT_7_INT_18,
      D => X_CNT_6(7),
      C => clk,
      CLR => rst_n_i);
  \II_x_cnt[8]\: FDC port map (
      Q => X_CNT_8_INT_19,
      D => X_CNT_6(8),
      C => clk,
      CLR => rst_n_i);
  \II_x_cnt[9]\: FDC port map (
      Q => X_CNT_9_INT_20,
      D => X_CNT_6(9),
      C => clk,
      CLR => rst_n_i);
  \II_y_cnt[0]\: FDC port map (
      Q => Y_CNT_0_INT_1,
      D => Y_CNT_6(0),
      C => clk,
      CLR => rst_n_i);
  \II_y_cnt[1]\: FDC port map (
      Q => Y_CNT_1_INT_2,
      D => UN1_Y_CNT_1_S_1_N,
      C => clk,
      CLR => rst_n_i);
  \II_y_cnt[2]\: FDC port map (
      Q => Y_CNT_2_INT_3,
      D => UN1_Y_CNT_1_S_2_N,
      C => clk,
      CLR => rst_n_i);
  \II_y_cnt[3]\: FDC port map (
      Q => Y_CNT_3_INT_4,
      D => Y_CNT_6(3),
      C => clk,
      CLR => rst_n_i);
  \II_y_cnt[4]\: FDC port map (