richic_vga_top.vhm

有关 VHDL进行VGA显示的源程序

--
-- Written by Synplicity
-- Sat Aug 20 20:31:29 2005
--

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity char_rom_rhic_1 is
port(
  char_sel : in std_logic_vector (8 downto 7);
  ypos : in std_logic_vector (4 downto 1);
  x_cnt : in std_logic_vector (6 downto 5);
  N_505_i :  out std_logic;
  N_506_i :  out std_logic;
  N_507_i :  out std_logic;
  N_508_i :  out std_logic;
  N_509_i :  out std_logic;
  N_510_i :  out std_logic;
  N_511_i :  out std_logic;
  N_512_i :  out std_logic;
  N_513_i :  out std_logic;
  N_514_i :  out std_logic;
  N_515_i :  out std_logic;
  N_516_i :  out std_logic;
  N_517_i :  out std_logic;
  N_518_i :  out std_logic;
  N_504_i :  out std_logic);
end char_rom_rhic_1;

architecture beh of char_rom_rhic_1 is
  signal DATA_1151_15_1 : std_logic ;
  signal DATA_1151_15 : std_logic ;
  signal DATA_1183_15 : std_logic ;
  signal DATA_1151_15_M_134_N : std_logic ;
  signal DATA_1_15RO_A_0_IV_0 : std_logic ;
  signal DATA_1183_15_M_133_N : std_logic ;
  signal DATA_14_15 : std_logic ;
  signal DATA_14_14 : std_logic ;
  signal DATA_1132_14 : std_logic ;
  signal DATA_14_13 : std_logic ;
  signal DATA_1132_13 : std_logic ;
  signal DATA_13_12 : std_logic ;
  signal DATA_1131_12 : std_logic ;
  signal DATA_14_11 : std_logic ;
  signal DATA_1132_11 : std_logic ;
  signal DATA_11_10 : std_logic ;
  signal DATA_1132_10 : std_logic ;
  signal DATA_12_9 : std_logic ;
  signal DATA_1129_9 : std_logic ;
  signal DATA_14_8 : std_logic ;
  signal DATA_1132_8 : std_logic ;
  signal DATA_16_7 : std_logic ;
  signal DATA_1132_7 : std_logic ;
  signal DATA_19_6 : std_logic ;
  signal DATA_1130_6 : std_logic ;
  signal DATA_10_5 : std_logic ;
  signal DATA_1130_5 : std_logic ;
  signal DATA_19_4 : std_logic ;
  signal DATA_1130_4 : std_logic ;
  signal DATA_12_3 : std_logic ;
  signal DATA_1130_3 : std_logic ;
  signal DATA_14_2 : std_logic ;
  signal DATA_1130_2 : std_logic ;
  signal DATA_19_1 : std_logic ;
  signal DATA_1132_1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  component ROM128X1
    generic(
      INIT : bit_vector
    );
    port(
      A0 : in std_logic;
      A1 : in std_logic;
      A2 : in std_logic;
      A3 : in std_logic;
      A4 : in std_logic;
      A5 : in std_logic;
      A6 : in std_logic;
      O : out std_logic  );
  end component;
  component ROM64X1
    generic(
      INIT : bit_vector
    );
    port(
      A0 : in std_logic;
      A1 : in std_logic;
      A2 : in std_logic;
      A3 : in std_logic;
      A4 : in std_logic;
      A5 : in std_logic;
      O : out std_logic  );
  end component;
begin
  II_data_1151_15: LUT4 
  generic map(
    INIT => X"8002"
  )
  port map (
    I0 => DATA_1151_15_1,
    I1 => x_cnt(5),
    I2 => x_cnt(6),
    I3 => ypos(1),
    O => DATA_1151_15);
  II_data_1151_15_1: LUT3_L 
  generic map(
    INIT => X"60"
  )
  port map (
    I0 => ypos(1),
    I1 => ypos(2),
    I2 => ypos(3),
    LO => DATA_1151_15_1);
  II_data_1183_15: LUT4 
  generic map(
    INIT => X"0280"
  )
  port map (
    I0 => x_cnt(5),
    I1 => x_cnt(6),
    I2 => ypos(1),
    I3 => ypos(2),
    O => DATA_1183_15);
  II_N_504_i: LUT4_L 
  generic map(
    INIT => X"B333"
  )
  port map (
    I0 => DATA_1151_15_M_134_N,
    I1 => DATA_1_15RO_A_0_IV_0,
    I2 => DATA_1151_15,
    I3 => char_sel(8),
    LO => N_504_i);
  II_data_1_15ro_a_0_iv_0: LUT4_L 
  generic map(
    INIT => X"5F13"
  )
  port map (
    I0 => DATA_1183_15_M_133_N,
    I1 => DATA_14_15,
    I2 => DATA_1183_15,
    I3 => char_sel(8),
    LO => DATA_1_15RO_A_0_IV_0);
  II_N_518_i: LUT4 
  generic map(
    INIT => X"0CAA"
  )
  port map (
    I0 => DATA_14_14,
    I1 => DATA_1132_14,
    I2 => char_sel(7),
    I3 => char_sel(8),
    O => N_518_i);
  II_N_517_i: LUT4 
  generic map(
    INIT => X"0CAA"
  )
  port map (
    I0 => DATA_14_13,
    I1 => DATA_1132_13,
    I2 => char_sel(7),
    I3 => char_sel(8),
    O => N_517_i);
  II_N_516_i: LUT4 
  generic map(
    INIT => X"0CAA"
  )
  port map (
    I0 => DATA_13_12,
    I1 => DATA_1131_12,
    I2 => char_sel(7),
    I3 => char_sel(8),
    O => N_516_i);
  II_N_515_i: LUT4 
  generic map(
    INIT => X"0CAA"
  )
  port map (
    I0 => DATA_14_11,
    I1 => DATA_1132_11,
    I2 => char_sel(7),
    I3 => char_sel(8),
    O => N_515_i);
  II_N_514_i: LUT4 
  generic map(
    INIT => X"0CAA"
  )
  port map (
    I0 => DATA_11_10,
    I1 => DATA_1132_10,
    I2 => char_sel(7),
    I3 => char_sel(8),
    O => N_514_i);
  II_N_513_i: LUT4 
  generic map(
    INIT => X"0CAA"
  )
  port map (
    I0 => DATA_12_9,
    I1 => DATA_1129_9,
    I2 => char_sel(7),
    I3 => char_sel(8),
    O => N_513_i);
  II_N_512_i: LUT4_L 
  generic map(
    INIT => X"0CAA"
  )
  port map (
    I0 => DATA_14_8,
    I1 => DATA_1132_8,
    I2 => char_sel(7),
    I3 => char_sel(8),
    LO => N_512_i);
  II_N_511_i: LUT4 
  generic map(
    INIT => X"0CAA"
  )
  port map (
    I0 => DATA_16_7,
    I1 => DATA_1132_7,
    I2 => char_sel(7),
    I3 => char_sel(8),
    O => N_511_i);
  II_N_510_i: LUT4 
  generic map(
    INIT => X"0CAA"
  )
  port map (
    I0 => DATA_19_6,
    I1 => DATA_1130_6,
    I2 => char_sel(7),
    I3 => char_sel(8),
    O => N_510_i);
  II_N_509_i: LUT4 
  generic map(
    INIT => X"0CAA"
  )
  port map (
    I0 => DATA_10_5,
    I1 => DATA_1130_5,
    I2 => char_sel(7),
    I3 => char_sel(8),
    O => N_509_i);
  II_N_508_i: LUT4 
  generic map(
    INIT => X"0CAA"
  )
  port map (
    I0 => DATA_19_4,
    I1 => DATA_1130_4,
    I2 => char_sel(7),
    I3 => char_sel(8),
    O => N_508_i);
  II_N_507_i: LUT4 
  generic map(
    INIT => X"0CAA"
  )
  port map (
    I0 => DATA_12_3,
    I1 => DATA_1130_3,
    I2 => char_sel(7),
    I3 => char_sel(8),
    O => N_507_i);
  II_N_506_i: LUT4 
  generic map(
    INIT => X"0CAA"
  )
  port map (
    I0 => DATA_14_2,
    I1 => DATA_1130_2,
    I2 => char_sel(7),
    I3 => char_sel(8),
    O => N_506_i);
  II_N_505_i: LUT4 
  generic map(
    INIT => X"0CAA"
  )
  port map (
    I0 => DATA_19_1,
    I1 => DATA_1132_1,
    I2 => char_sel(7),
    I3 => char_sel(8),
    O => N_505_i);
  II_data_1151_15_m_134: LUT4 
  generic map(
    INIT => X"3772"
  )
  port map (
    I0 => char_sel(7),
    I1 => char_sel(8),
    I2 => ypos(3),
    I3 => ypos(4),
    O => DATA_1151_15_M_134_N);
  II_data_1183_15_m_133: LUT4 
  generic map(
    INIT => X"4000"
  )
  port map (
    I0 => char_sel(7),
    I1 => char_sel(8),
    I2 => ypos(3),
    I3 => ypos(4),
    O => DATA_1183_15_M_133_N);
  II_data_14_15: ROM128X1 
  generic map(
    INIT => X"0B000444404030000003004800148100"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    A6 => char_sel(7),
    O => DATA_14_15);
  II_data_1132_14: ROM64X1 
  generic map(
    INIT => X"0A500800081A0100"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    O => DATA_1132_14);
  II_data_14_14: ROM128X1 
  generic map(
    INIT => X"0B0FF3B3373730000081262800148520"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    A6 => char_sel(7),
    O => DATA_14_14);
  II_data_1132_13: ROM64X1 
  generic map(
    INIT => X"0D02080C0A12A7A0"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    O => DATA_1132_13);
  II_data_14_13: ROM128X1 
  generic map(
    INIT => X"0F00080A9080700080001115D1159530"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    A6 => char_sel(7),
    O => DATA_14_13);
  II_data_1131_12: ROM64X1 
  generic map(
    INIT => X"200D2C048C120D08"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    O => DATA_1131_12);
  II_data_13_12: ROM128X1 
  generic map(
    INIT => X"040008021808F000088898888CDC8DA8"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    A6 => char_sel(7),
    O => DATA_13_12);
  II_data_1132_11: ROM64X1 
  generic map(
    INIT => X"20085A364C960500"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    O => DATA_1132_11);
  II_data_14_11: ROM128X1 
  generic map(
    INIT => X"04000D03999070004646667664D4C560"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    A6 => char_sel(7),
    O => DATA_14_11);
  II_data_1132_10: ROM64X1 
  generic map(
    INIT => X"80280947773B5510"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    O => DATA_1132_10);
  II_data_11_10: ROM128X1 
  generic map(
    INIT => X"08044CCA0404700000A000000846A226"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    A6 => char_sel(7),
    O => DATA_11_10);
  II_data_1129_9: ROM64X1 
  generic map(
    INIT => X"00E00224A45227E2"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    O => DATA_1129_9);
  II_data_12_9: ROM128X1 
  generic map(
    INIT => X"080884002223000011B1115142140024"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    A6 => char_sel(7),
    O => DATA_12_9);
  II_data_1132_8: ROM64X1 
  generic map(
    INIT => X"4A082004A4D20580"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    O => DATA_1132_8);
  II_data_14_8: ROM128X1 
  generic map(
    INIT => X"080000000000000008200041A0B19130"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    A6 => char_sel(7),
    O => DATA_14_8);
  II_data_1132_7: ROM64X1 
  generic map(
    INIT => X"0446CCCCAC120580"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    O => DATA_1132_7);
  II_data_16_7: ROM128X1 
  generic map(
    INIT => X"000000000000000000280A4B24918420"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    A6 => char_sel(7),
    O => DATA_16_7);
  II_data_1130_6: ROM64X1 
  generic map(
    INIT => X"02002004A01E838C"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    O => DATA_1130_6);
  II_data_19_6: ROM128X1 
  generic map(
    INIT => X"00000000000000000131959150D1C060"
  )
  port map (
    A0 => x_cnt(5),
    A1 => x_cnt(6),
    A2 => ypos(2),
    A3 => ypos(1),
    A4 => ypos(3),
    A5 => ypos(4),
    A6 => char_sel(7),
    O => DATA_19_6);