richic_vga_top.srd

有关 VHDL进行VGA显示的源程序

f "noname"; #file 0
f "d:\program files\synplicity\synplify_75\bin\..\lib\xilinx\unisim.v"; #file 1
f "e:\demo\pro017_vga\rtl\sync_gen_50m.v"; #file 2
f "e:\demo\pro017_vga\ise63_pro\ram1024x8.v"; #file 3
f "e:\demo\pro017_vga\ise63_pro\rom2048x8.v"; #file 4
f "e:\demo\pro017_vga\rtl\char_rom_rhic.v"; #file 5
f "e:\demo\pro017_vga\rtl\richic_vga_top.v"; #file 6
VNAME 'work.rom2048x8.verilog'; # view id 0
VNAME 'work.ram1024x8.verilog'; # view id 1
VNAME 'work.sync_gen_50m.verilog'; # view id 2
VNAME 'work.richic_vga_top.verilog'; # view id 3
VNAME 'work.char_rom_rhic.verilog'; # view id 4
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