📄 control.rpt
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_EQ010 = _LC4_B24 & !_LC5_B24
# _LC3_B24 & !_LC4_B24 & _LC5_B24
# !_LC2_B24 & !_LC4_B24 & _LC5_B24;
-- Node name is '|clkgen:u0|div10:clk1M|:4' = '|clkgen:u0|div10:clk1M|qs2'
-- Equation name is '_LC3_B24', type is buried
_LC3_B24 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = _LC3_B24 & !_LC5_B24
# !_LC3_B24 & _LC4_B24 & _LC5_B24
# _LC3_B24 & !_LC4_B24;
-- Node name is '|clkgen:u0|div10:clk1M|:3' = '|clkgen:u0|div10:clk1M|qs3'
-- Equation name is '_LC2_B24', type is buried
_LC2_B24 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = _LC2_B24 & !_LC5_B24
# !_LC2_B24 & _LC3_B24 & _LC4_B24 & _LC5_B24
# _LC2_B24 & !_LC3_B24 & _LC4_B24
# _LC2_B24 & _LC3_B24 & !_LC4_B24;
-- Node name is '|clkgen:u0|div10:clk10|:7' = '|clkgen:u0|div10:clk10|ca'
-- Equation name is '_LC8_B23', type is buried
_LC8_B23 = DFFE( _EQ013, _LC3_B21, VCC, VCC, VCC);
_EQ013 = _LC1_B21 & !_LC1_B23 & _LC2_B23 & !_LC8_B21;
-- Node name is '|clkgen:u0|div10:clk10|:6' = '|clkgen:u0|div10:clk10|qs0'
-- Equation name is '_LC1_B21', type is buried
_LC1_B21 = DFFE(!_LC1_B21, _LC3_B21, VCC, VCC, VCC);
-- Node name is '|clkgen:u0|div10:clk10|:5' = '|clkgen:u0|div10:clk10|qs1'
-- Equation name is '_LC1_B23', type is buried
_LC1_B23 = DFFE( _EQ014, _LC3_B21, VCC, VCC, VCC);
_EQ014 = !_LC1_B21 & _LC1_B23
# _LC1_B21 & !_LC1_B23 & _LC8_B21
# _LC1_B21 & !_LC1_B23 & !_LC2_B23;
-- Node name is '|clkgen:u0|div10:clk10|:4' = '|clkgen:u0|div10:clk10|qs2'
-- Equation name is '_LC8_B21', type is buried
_LC8_B21 = DFFE( _EQ015, _LC3_B21, VCC, VCC, VCC);
_EQ015 = !_LC1_B21 & _LC8_B21
# _LC1_B21 & _LC1_B23 & !_LC8_B21
# !_LC1_B23 & _LC8_B21;
-- Node name is '|clkgen:u0|div10:clk10|:3' = '|clkgen:u0|div10:clk10|qs3'
-- Equation name is '_LC2_B23', type is buried
_LC2_B23 = DFFE( _EQ016, _LC3_B21, VCC, VCC, VCC);
_EQ016 = !_LC1_B21 & _LC2_B23
# _LC1_B21 & _LC1_B23 & !_LC2_B23 & _LC8_B21
# _LC1_B23 & _LC2_B23 & !_LC8_B21
# !_LC1_B23 & _LC2_B23 & _LC8_B21;
-- Node name is '|clkgen:u0|div10:clk10K|:7' = '|clkgen:u0|div10:clk10K|ca'
-- Equation name is '_LC8_B20', type is buried
_LC8_B20 = DFFE( _EQ017, _LC1_B22, VCC, VCC, VCC);
_EQ017 = !_LC1_B20 & _LC3_B20 & _LC3_B22 & !_LC8_B22;
-- Node name is '|clkgen:u0|div10:clk10K|:6' = '|clkgen:u0|div10:clk10K|qs0'
-- Equation name is '_LC3_B22', type is buried
_LC3_B22 = DFFE(!_LC3_B22, _LC1_B22, VCC, VCC, VCC);
-- Node name is '|clkgen:u0|div10:clk10K|:5' = '|clkgen:u0|div10:clk10K|qs1'
-- Equation name is '_LC1_B20', type is buried
_LC1_B20 = DFFE( _EQ018, _LC1_B22, VCC, VCC, VCC);
_EQ018 = _LC1_B20 & !_LC3_B22
# !_LC1_B20 & _LC3_B22 & _LC8_B22
# !_LC1_B20 & !_LC3_B20 & _LC3_B22;
-- Node name is '|clkgen:u0|div10:clk10K|:4' = '|clkgen:u0|div10:clk10K|qs2'
-- Equation name is '_LC8_B22', type is buried
_LC8_B22 = DFFE( _EQ019, _LC1_B22, VCC, VCC, VCC);
_EQ019 = !_LC3_B22 & _LC8_B22
# _LC1_B20 & _LC3_B22 & !_LC8_B22
# !_LC1_B20 & _LC8_B22;
-- Node name is '|clkgen:u0|div10:clk10K|:3' = '|clkgen:u0|div10:clk10K|qs3'
-- Equation name is '_LC3_B20', type is buried
_LC3_B20 = DFFE( _EQ020, _LC1_B22, VCC, VCC, VCC);
_EQ020 = _LC3_B20 & !_LC3_B22
# _LC1_B20 & !_LC3_B20 & _LC3_B22 & _LC8_B22
# _LC1_B20 & _LC3_B20 & !_LC8_B22
# !_LC1_B20 & _LC3_B20 & _LC8_B22;
-- Node name is '|clkgen:u0|div10:clk100|:7' = '|clkgen:u0|div10:clk100|ca'
-- Equation name is '_LC3_B21', type is buried
_LC3_B21 = DFFE( _EQ021, _LC2_B20, VCC, VCC, VCC);
_EQ021 = _LC2_B21 & !_LC4_B21 & !_LC5_B21 & _LC6_B21;
-- Node name is '|clkgen:u0|div10:clk100|:6' = '|clkgen:u0|div10:clk100|qs0'
-- Equation name is '_LC6_B21', type is buried
_LC6_B21 = DFFE(!_LC6_B21, _LC2_B20, VCC, VCC, VCC);
-- Node name is '|clkgen:u0|div10:clk100|:5' = '|clkgen:u0|div10:clk100|qs1'
-- Equation name is '_LC5_B21', type is buried
_LC5_B21 = DFFE( _EQ022, _LC2_B20, VCC, VCC, VCC);
_EQ022 = _LC5_B21 & !_LC6_B21
# _LC4_B21 & !_LC5_B21 & _LC6_B21
# !_LC2_B21 & !_LC5_B21 & _LC6_B21;
-- Node name is '|clkgen:u0|div10:clk100|:4' = '|clkgen:u0|div10:clk100|qs2'
-- Equation name is '_LC4_B21', type is buried
_LC4_B21 = DFFE( _EQ023, _LC2_B20, VCC, VCC, VCC);
_EQ023 = _LC4_B21 & !_LC6_B21
# !_LC4_B21 & _LC5_B21 & _LC6_B21
# _LC4_B21 & !_LC5_B21;
-- Node name is '|clkgen:u0|div10:clk100|:3' = '|clkgen:u0|div10:clk100|qs3'
-- Equation name is '_LC2_B21', type is buried
_LC2_B21 = DFFE( _EQ024, _LC2_B20, VCC, VCC, VCC);
_EQ024 = _LC2_B21 & !_LC6_B21
# !_LC2_B21 & _LC4_B21 & _LC5_B21 & _LC6_B21
# _LC2_B21 & !_LC4_B21 & _LC5_B21
# _LC2_B21 & _LC4_B21 & !_LC5_B21;
-- Node name is '|clkgen:u0|div10:clk100K|:7' = '|clkgen:u0|div10:clk100K|ca'
-- Equation name is '_LC1_B22', type is buried
_LC1_B22 = DFFE( _EQ025, _LC1_B24, VCC, VCC, VCC);
_EQ025 = _LC2_B22 & !_LC4_B22 & !_LC5_B22 & _LC6_B22;
-- Node name is '|clkgen:u0|div10:clk100K|:6' = '|clkgen:u0|div10:clk100K|qs0'
-- Equation name is '_LC6_B22', type is buried
_LC6_B22 = DFFE(!_LC6_B22, _LC1_B24, VCC, VCC, VCC);
-- Node name is '|clkgen:u0|div10:clk100K|:5' = '|clkgen:u0|div10:clk100K|qs1'
-- Equation name is '_LC5_B22', type is buried
_LC5_B22 = DFFE( _EQ026, _LC1_B24, VCC, VCC, VCC);
_EQ026 = _LC5_B22 & !_LC6_B22
# _LC4_B22 & !_LC5_B22 & _LC6_B22
# !_LC2_B22 & !_LC5_B22 & _LC6_B22;
-- Node name is '|clkgen:u0|div10:clk100K|:4' = '|clkgen:u0|div10:clk100K|qs2'
-- Equation name is '_LC4_B22', type is buried
_LC4_B22 = DFFE( _EQ027, _LC1_B24, VCC, VCC, VCC);
_EQ027 = _LC4_B22 & !_LC6_B22
# !_LC4_B22 & _LC5_B22 & _LC6_B22
# _LC4_B22 & !_LC5_B22;
-- Node name is '|clkgen:u0|div10:clk100K|:3' = '|clkgen:u0|div10:clk100K|qs3'
-- Equation name is '_LC2_B22', type is buried
_LC2_B22 = DFFE( _EQ028, _LC1_B24, VCC, VCC, VCC);
_EQ028 = _LC2_B22 & !_LC6_B22
# !_LC2_B22 & _LC4_B22 & _LC5_B22 & _LC6_B22
# _LC2_B22 & !_LC4_B22 & _LC5_B22
# _LC2_B22 & _LC4_B22 & !_LC5_B22;
-- Node name is '|traffic:u1|:10' = '|traffic:u1|current_state0'
-- Equation name is '_LC8_A23', type is buried
_LC8_A23 = DFFE( _LC4_A23, _LC4_B23, VCC, VCC, clrn);
-- Node name is '|traffic:u1|:9' = '|traffic:u1|current_state1'
-- Equation name is '_LC7_A23', type is buried
_LC7_A23 = DFFE( _LC1_A23, _LC4_B23, VCC, VCC, clrn);
-- Node name is '|traffic:u1|:12' = '|traffic:u1|next_state0'
-- Equation name is '_LC4_A23', type is buried
_LC4_A23 = DFFE(!_LC8_A23, _LC4_B23, VCC, VCC, clrn);
-- Node name is '|traffic:u1|:11' = '|traffic:u1|next_state1'
-- Equation name is '_LC1_A23', type is buried
_LC1_A23 = DFFE( _EQ029, _LC4_B23, VCC, VCC, clrn);
_EQ029 = _LC7_A23 & !_LC8_A23
# !_LC7_A23 & _LC8_A23;
-- Node name is '|traffic:u1|:18' = '|traffic:u1|qs_lights0'
-- Equation name is '_LC4_A19', type is buried
_LC4_A19 = DFFE(!_LC7_A23, _LC4_B23, VCC, VCC, clrn);
-- Node name is '|traffic:u1|:17' = '|traffic:u1|qs_lights1'
-- Equation name is '_LC5_A23', type is buried
_LC5_A23 = DFFE( _EQ030, _LC4_B23, VCC, VCC, clrn);
_EQ030 = _LC7_A23 & _LC8_A23;
-- Node name is '|traffic:u1|:16' = '|traffic:u1|qs_lights2'
-- Equation name is '_LC6_A23', type is buried
_LC6_A23 = DFFE( _EQ031, _LC4_B23, VCC, VCC, clrn);
_EQ031 = _LC7_A23 & !_LC8_A23;
-- Node name is '|traffic:u1|:15' = '|traffic:u1|qs_lights3'
-- Equation name is '_LC1_A19', type is buried
_LC1_A19 = DFFE( _LC7_A23, _LC4_B23, VCC, VCC, clrn);
-- Node name is '|traffic:u1|:14' = '|traffic:u1|qs_lights4'
-- Equation name is '_LC2_A23', type is buried
_LC2_A23 = DFFE( _EQ032, _LC4_B23, VCC, VCC, clrn);
_EQ032 = !_LC7_A23 & _LC8_A23;
-- Node name is '|traffic:u1|:13' = '|traffic:u1|qs_lights5'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = DFFE( _EQ033, _LC4_B23, VCC, VCC, clrn);
_EQ033 = !_LC7_A23 & !_LC8_A23;
Project Information d:\test\control.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 11,203K
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