📄 control.rpt
字号:
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G 0 0 0 0 clk
47 - - - 16 INPUT 0 0 0 10 clrn
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\test\control.rpt
control
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
9 - - A -- OUTPUT 0 1 0 0 hg
7 - - A -- OUTPUT 0 1 0 0 hr
8 - - A -- OUTPUT 0 1 0 0 hy
141 - - - 22 OUTPUT 0 0 0 0 LED_COM
12 - - A -- OUTPUT 0 1 0 0 vg
10 - - A -- OUTPUT 0 1 0 0 vr
11 - - A -- OUTPUT 0 1 0 0 vy
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\test\control.rpt
control
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 23 DFFE 0 4 0 2 |clkgen:u0|div10:clk1|qs3 (|clkgen:u0|div10:clk1|:3)
- 5 - B 23 DFFE 0 3 0 3 |clkgen:u0|div10:clk1|qs2 (|clkgen:u0|div10:clk1|:4)
- 6 - B 23 DFFE 0 4 0 3 |clkgen:u0|div10:clk1|qs1 (|clkgen:u0|div10:clk1|:5)
- 7 - B 23 DFFE 0 1 0 4 |clkgen:u0|div10:clk1|qs0 (|clkgen:u0|div10:clk1|:6)
- 4 - B 23 DFFE 0 5 0 10 |clkgen:u0|div10:clk1|ca (|clkgen:u0|div10:clk1|:7)
- 4 - B 20 DFFE 0 4 0 2 |clkgen:u0|div10:clk1K|qs3 (|clkgen:u0|div10:clk1K|:3)
- 5 - B 20 DFFE 0 3 0 3 |clkgen:u0|div10:clk1K|qs2 (|clkgen:u0|div10:clk1K|:4)
- 6 - B 20 DFFE 0 4 0 3 |clkgen:u0|div10:clk1K|qs1 (|clkgen:u0|div10:clk1K|:5)
- 7 - B 20 DFFE 0 1 0 4 |clkgen:u0|div10:clk1K|qs0 (|clkgen:u0|div10:clk1K|:6)
- 2 - B 20 DFFE 0 5 0 5 |clkgen:u0|div10:clk1K|ca (|clkgen:u0|div10:clk1K|:7)
- 2 - B 24 DFFE + 0 3 0 2 |clkgen:u0|div10:clk1M|qs3 (|clkgen:u0|div10:clk1M|:3)
- 3 - B 24 DFFE + 0 2 0 3 |clkgen:u0|div10:clk1M|qs2 (|clkgen:u0|div10:clk1M|:4)
- 4 - B 24 DFFE + 0 3 0 3 |clkgen:u0|div10:clk1M|qs1 (|clkgen:u0|div10:clk1M|:5)
- 5 - B 24 DFFE + 0 0 0 4 |clkgen:u0|div10:clk1M|qs0 (|clkgen:u0|div10:clk1M|:6)
- 1 - B 24 DFFE + 0 4 0 5 |clkgen:u0|div10:clk1M|ca (|clkgen:u0|div10:clk1M|:7)
- 2 - B 23 DFFE 0 4 0 2 |clkgen:u0|div10:clk10|qs3 (|clkgen:u0|div10:clk10|:3)
- 8 - B 21 DFFE 0 3 0 3 |clkgen:u0|div10:clk10|qs2 (|clkgen:u0|div10:clk10|:4)
- 1 - B 23 DFFE 0 4 0 3 |clkgen:u0|div10:clk10|qs1 (|clkgen:u0|div10:clk10|:5)
- 1 - B 21 DFFE 0 1 0 4 |clkgen:u0|div10:clk10|qs0 (|clkgen:u0|div10:clk10|:6)
- 8 - B 23 DFFE 0 5 0 5 |clkgen:u0|div10:clk10|ca (|clkgen:u0|div10:clk10|:7)
- 3 - B 20 DFFE 0 4 0 2 |clkgen:u0|div10:clk10K|qs3 (|clkgen:u0|div10:clk10K|:3)
- 8 - B 22 DFFE 0 3 0 3 |clkgen:u0|div10:clk10K|qs2 (|clkgen:u0|div10:clk10K|:4)
- 1 - B 20 DFFE 0 4 0 3 |clkgen:u0|div10:clk10K|qs1 (|clkgen:u0|div10:clk10K|:5)
- 3 - B 22 DFFE 0 1 0 4 |clkgen:u0|div10:clk10K|qs0 (|clkgen:u0|div10:clk10K|:6)
- 8 - B 20 DFFE 0 5 0 5 |clkgen:u0|div10:clk10K|ca (|clkgen:u0|div10:clk10K|:7)
- 2 - B 21 DFFE 0 4 0 2 |clkgen:u0|div10:clk100|qs3 (|clkgen:u0|div10:clk100|:3)
- 4 - B 21 DFFE 0 3 0 3 |clkgen:u0|div10:clk100|qs2 (|clkgen:u0|div10:clk100|:4)
- 5 - B 21 DFFE 0 4 0 3 |clkgen:u0|div10:clk100|qs1 (|clkgen:u0|div10:clk100|:5)
- 6 - B 21 DFFE 0 1 0 4 |clkgen:u0|div10:clk100|qs0 (|clkgen:u0|div10:clk100|:6)
- 3 - B 21 DFFE 0 5 0 5 |clkgen:u0|div10:clk100|ca (|clkgen:u0|div10:clk100|:7)
- 2 - B 22 DFFE 0 4 0 2 |clkgen:u0|div10:clk100K|qs3 (|clkgen:u0|div10:clk100K|:3)
- 4 - B 22 DFFE 0 3 0 3 |clkgen:u0|div10:clk100K|qs2 (|clkgen:u0|div10:clk100K|:4)
- 5 - B 22 DFFE 0 4 0 3 |clkgen:u0|div10:clk100K|qs1 (|clkgen:u0|div10:clk100K|:5)
- 6 - B 22 DFFE 0 1 0 4 |clkgen:u0|div10:clk100K|qs0 (|clkgen:u0|div10:clk100K|:6)
- 1 - B 22 DFFE 0 5 0 5 |clkgen:u0|div10:clk100K|ca (|clkgen:u0|div10:clk100K|:7)
- 7 - A 23 DFFE 1 2 0 7 |traffic:u1|current_state1 (|traffic:u1|:9)
- 8 - A 23 DFFE 1 2 0 6 |traffic:u1|current_state0 (|traffic:u1|:10)
- 1 - A 23 DFFE 1 3 0 1 |traffic:u1|next_state1 (|traffic:u1|:11)
- 4 - A 23 DFFE 1 2 0 1 |traffic:u1|next_state0 (|traffic:u1|:12)
- 3 - A 23 DFFE 1 3 1 0 |traffic:u1|qs_lights5 (|traffic:u1|:13)
- 2 - A 23 DFFE 1 3 1 0 |traffic:u1|qs_lights4 (|traffic:u1|:14)
- 1 - A 19 DFFE 1 2 1 0 |traffic:u1|qs_lights3 (|traffic:u1|:15)
- 6 - A 23 DFFE 1 3 1 0 |traffic:u1|qs_lights2 (|traffic:u1|:16)
- 5 - A 23 DFFE 1 3 1 0 |traffic:u1|qs_lights1 (|traffic:u1|:17)
- 4 - A 19 DFFE 1 2 1 0 |traffic:u1|qs_lights0 (|traffic:u1|:18)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\test\control.rpt
control
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 8/ 48( 16%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 10/ 48( 20%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\test\control.rpt
control
** CLOCK SIGNALS **
Type Fan-out Name
DFF 10 |clkgen:u0|div10:clk1|ca
INPUT 5 clk
DFF 5 |clkgen:u0|div10:clk1K|ca
DFF 5 |clkgen:u0|div10:clk1M|ca
DFF 5 |clkgen:u0|div10:clk10|ca
DFF 5 |clkgen:u0|div10:clk10K|ca
DFF 5 |clkgen:u0|div10:clk100|ca
DFF 5 |clkgen:u0|div10:clk100K|ca
Device-Specific Information: d:\test\control.rpt
control
** EQUATIONS **
clk : INPUT;
clrn : INPUT;
-- Node name is 'hg'
-- Equation name is 'hg', type is output
hg = _LC3_A23;
-- Node name is 'hr'
-- Equation name is 'hr', type is output
hr = _LC1_A19;
-- Node name is 'hy'
-- Equation name is 'hy', type is output
hy = _LC2_A23;
-- Node name is 'LED_COM'
-- Equation name is 'LED_COM', type is output
LED_COM = VCC;
-- Node name is 'vg'
-- Equation name is 'vg', type is output
vg = _LC6_A23;
-- Node name is 'vr'
-- Equation name is 'vr', type is output
vr = _LC4_A19;
-- Node name is 'vy'
-- Equation name is 'vy', type is output
vy = _LC5_A23;
-- Node name is '|clkgen:u0|div10:clk1|:7' = '|clkgen:u0|div10:clk1|ca'
-- Equation name is '_LC4_B23', type is buried
_LC4_B23 = DFFE( _EQ001, _LC8_B23, VCC, VCC, VCC);
_EQ001 = _LC3_B23 & !_LC5_B23 & !_LC6_B23 & _LC7_B23;
-- Node name is '|clkgen:u0|div10:clk1|:6' = '|clkgen:u0|div10:clk1|qs0'
-- Equation name is '_LC7_B23', type is buried
_LC7_B23 = DFFE(!_LC7_B23, _LC8_B23, VCC, VCC, VCC);
-- Node name is '|clkgen:u0|div10:clk1|:5' = '|clkgen:u0|div10:clk1|qs1'
-- Equation name is '_LC6_B23', type is buried
_LC6_B23 = DFFE( _EQ002, _LC8_B23, VCC, VCC, VCC);
_EQ002 = _LC6_B23 & !_LC7_B23
# _LC5_B23 & !_LC6_B23 & _LC7_B23
# !_LC3_B23 & !_LC6_B23 & _LC7_B23;
-- Node name is '|clkgen:u0|div10:clk1|:4' = '|clkgen:u0|div10:clk1|qs2'
-- Equation name is '_LC5_B23', type is buried
_LC5_B23 = DFFE( _EQ003, _LC8_B23, VCC, VCC, VCC);
_EQ003 = _LC5_B23 & !_LC7_B23
# !_LC5_B23 & _LC6_B23 & _LC7_B23
# _LC5_B23 & !_LC6_B23;
-- Node name is '|clkgen:u0|div10:clk1|:3' = '|clkgen:u0|div10:clk1|qs3'
-- Equation name is '_LC3_B23', type is buried
_LC3_B23 = DFFE( _EQ004, _LC8_B23, VCC, VCC, VCC);
_EQ004 = _LC3_B23 & !_LC7_B23
# !_LC3_B23 & _LC5_B23 & _LC6_B23 & _LC7_B23
# _LC3_B23 & !_LC5_B23 & _LC6_B23
# _LC3_B23 & _LC5_B23 & !_LC6_B23;
-- Node name is '|clkgen:u0|div10:clk1K|:7' = '|clkgen:u0|div10:clk1K|ca'
-- Equation name is '_LC2_B20', type is buried
_LC2_B20 = DFFE( _EQ005, _LC8_B20, VCC, VCC, VCC);
_EQ005 = _LC4_B20 & !_LC5_B20 & !_LC6_B20 & _LC7_B20;
-- Node name is '|clkgen:u0|div10:clk1K|:6' = '|clkgen:u0|div10:clk1K|qs0'
-- Equation name is '_LC7_B20', type is buried
_LC7_B20 = DFFE(!_LC7_B20, _LC8_B20, VCC, VCC, VCC);
-- Node name is '|clkgen:u0|div10:clk1K|:5' = '|clkgen:u0|div10:clk1K|qs1'
-- Equation name is '_LC6_B20', type is buried
_LC6_B20 = DFFE( _EQ006, _LC8_B20, VCC, VCC, VCC);
_EQ006 = _LC6_B20 & !_LC7_B20
# _LC5_B20 & !_LC6_B20 & _LC7_B20
# !_LC4_B20 & !_LC6_B20 & _LC7_B20;
-- Node name is '|clkgen:u0|div10:clk1K|:4' = '|clkgen:u0|div10:clk1K|qs2'
-- Equation name is '_LC5_B20', type is buried
_LC5_B20 = DFFE( _EQ007, _LC8_B20, VCC, VCC, VCC);
_EQ007 = _LC5_B20 & !_LC7_B20
# !_LC5_B20 & _LC6_B20 & _LC7_B20
# _LC5_B20 & !_LC6_B20;
-- Node name is '|clkgen:u0|div10:clk1K|:3' = '|clkgen:u0|div10:clk1K|qs3'
-- Equation name is '_LC4_B20', type is buried
_LC4_B20 = DFFE( _EQ008, _LC8_B20, VCC, VCC, VCC);
_EQ008 = _LC4_B20 & !_LC7_B20
# !_LC4_B20 & _LC5_B20 & _LC6_B20 & _LC7_B20
# _LC4_B20 & !_LC5_B20 & _LC6_B20
# _LC4_B20 & _LC5_B20 & !_LC6_B20;
-- Node name is '|clkgen:u0|div10:clk1M|:7' = '|clkgen:u0|div10:clk1M|ca'
-- Equation name is '_LC1_B24', type is buried
_LC1_B24 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = _LC2_B24 & !_LC3_B24 & !_LC4_B24 & _LC5_B24;
-- Node name is '|clkgen:u0|div10:clk1M|:6' = '|clkgen:u0|div10:clk1M|qs0'
-- Equation name is '_LC5_B24', type is buried
_LC5_B24 = DFFE(!_LC5_B24, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|clkgen:u0|div10:clk1M|:5' = '|clkgen:u0|div10:clk1M|qs1'
-- Equation name is '_LC4_B24', type is buried
_LC4_B24 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
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