div10.vhd

个人硬件课程设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity div10 is 
  port(clk :in std_logic;
             outclk:out std_logic);
end div10;

architecture div10 of div10 is
   signal qs: std_logic_vector(3 downto 0);
   signal ca:std_logic;
begin  
   process (clk)
begin 
   if(clk'event and clk='1')then
      if (qs="1001")then
  qs<="0000";
  ca<='1';
else 
  qs<=qs+'1';
  ca<='0';
     end  if ;
    end  if;
  end process;
  outclk<=ca;
end div10;