traffic.rpt

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 (40)    18    B       DFFE   +  t        0      0   0    1    1    4    2  current_state0 (:10)
 (41)    17    B       DFFE   +  t        0      0   0    1    2    0    1  next_state1 (:11)
 (31)    26    B       DFFE   +  t        0      0   0    1    1    0    1  next_state0 (:12)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                               d:\test\traffic.rpt
traffic

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                             Logic cells placed in LAB 'B'
        +------------------- LC25 hg
        | +----------------- LC24 hr
        | | +--------------- LC23 hy
        | | | +------------- LC22 vg
        | | | | +----------- LC21 vr
        | | | | | +--------- LC20 vy
        | | | | | | +------- LC19 current_state1
        | | | | | | | +----- LC18 current_state0
        | | | | | | | | +--- LC17 next_state1
        | | | | | | | | | +- LC26 next_state0
        | | | | | | | | | | 
        | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC19 -> * * * * * * - - * - | - * | <-- current_state1
LC18 -> * - * * - * - - * * | - * | <-- current_state0
LC17 -> - - - - - - * - - - | - * | <-- next_state1
LC26 -> - - - - - - - * - - | - * | <-- next_state0

Pin
43   -> - - - - - - - - - - | - - | <-- clkin
4    -> * * * * * * * * * * | - * | <-- clrn


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               d:\test\traffic.rpt
traffic

** EQUATIONS **

clkin    : INPUT;
clrn     : INPUT;

-- Node name is ':10' = 'current_state0' 
-- Equation name is 'current_state0', location is LC018, type is buried.
current_state0 = DFFE( next_state0 $  GND, GLOBAL( clkin),  VCC,  VCC,  clrn);

-- Node name is ':9' = 'current_state1' 
-- Equation name is 'current_state1', location is LC019, type is buried.
current_state1 = DFFE( next_state1 $  GND, GLOBAL( clkin),  VCC,  VCC,  clrn);

-- Node name is 'hg' = 'qs_lights5' 
-- Equation name is 'hg', location is LC025, type is output.
 hg      = DFFE( _EQ001 $ !current_state1, GLOBAL( clkin),  VCC,  VCC,  clrn);
  _EQ001 =  current_state0 & !current_state1;

-- Node name is 'hr' = 'qs_lights3' 
-- Equation name is 'hr', location is LC024, type is output.
 hr      = DFFE(!current_state1 $  VCC, GLOBAL( clkin),  VCC,  VCC,  clrn);

-- Node name is 'hy' = 'qs_lights4' 
-- Equation name is 'hy', location is LC023, type is output.
 hy      = DFFE( _EQ002 $  current_state0, GLOBAL( clkin),  VCC,  VCC,  clrn);
  _EQ002 =  current_state0 &  current_state1;

-- Node name is ':12' = 'next_state0' 
-- Equation name is 'next_state0', location is LC026, type is buried.
next_state0 = DFFE( current_state0 $  VCC, GLOBAL( clkin),  VCC,  VCC,  clrn);

-- Node name is ':11' = 'next_state1' 
-- Equation name is 'next_state1', location is LC017, type is buried.
next_state1 = DFFE( current_state0 $  current_state1, GLOBAL( clkin),  VCC,  VCC,  clrn);

-- Node name is 'vg' = 'qs_lights2' 
-- Equation name is 'vg', location is LC022, type is output.
 vg      = DFFE( _EQ003 $  current_state1, GLOBAL( clkin),  VCC,  VCC,  clrn);
  _EQ003 =  current_state0 &  current_state1;

-- Node name is 'vr' = 'qs_lights0' 
-- Equation name is 'vr', location is LC021, type is output.
 vr      = DFFE( current_state1 $  VCC, GLOBAL( clkin),  VCC,  VCC,  clrn);

-- Node name is 'vy' = 'qs_lights1' 
-- Equation name is 'vy', location is LC020, type is output.
 vy      = DFFE( _EQ004 $  current_state0, GLOBAL( clkin),  VCC,  VCC,  clrn);
  _EQ004 =  current_state0 & !current_state1;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        d:\test\traffic.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,912K