control.vhd

个人硬件课程设计

library ieee;
use ieee.std_logic_1164.all;


entity control is
   port (clk :in std_logic;
          clrn:in std_logic;
          hg: out std_logic;
          hy: out std_logic; 
          hr: out std_logic; 
          vg: out std_logic; 
          vy: out std_logic; 
          vr: out std_logic;
          LED_COM : out std_logic);
end control;


architecture  control of control is
   component clkgen
      port(clk:in std_logic;
             outclk_1M,
             outclk_100K,
             outclk_10K,
             outclk_1K,
             outclk_100,
             outclk_10,
             outclk_1: out std_logic);
  end  component;
 
component traffic 
  port(   clkin: in std_logic;
          clrn: in std_logic;
          hg: out std_logic;
          hy: out std_logic; 
          hr: out std_logic; 
          vg: out std_logic; 
          vy: out std_logic; 
          vr: out std_logic);
  end component;


signal qs_clk1:std_logic;
  begin
   u0:clkgen port map(clk=>clk,
                       outclk_1=>qs_clk1 );
   u1:traffic port map(clkin=>qs_clk1,
                     clrn=>clrn,
                     hg=>hg,
                     hy=>hy,
                     hr=>hr,
                     vg=>vg,
                     vy=>vy,
                     vr=>vr);
   LED_COM<='1';
 end control;