clkgen.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clkgen is
   port(clk:in std_logic;
        outclk_1M,
        outclk_100K , 
        outclk_10K , 
        outclk_1K ,
        outclk_100 , 
        outclk_10 ,  
        outclk_1 :out std_logic   );
end clkgen;


architecture clkgen of clkgen is
component div10
  port (clk:in std_logic;
        outclk :out std_logic);
end component;
signal ca_1M,
       ca_100K,
       ca_10K,
       ca_1K,
       ca_100,
       ca_10,
       ca_1:std_logic;
begin 
clk1M:div10 port map (clk=>clk,
                             outclk=>ca_1M);
clk100K:div10 port map (clk=>ca_1M,
                             outclk=>ca_100K);

clk10K:div10 port map (clk=>ca_100K,
                             outclk=>ca_10K);

clk1K:div10 port map (clk=>ca_10K,
                             outclk=>ca_1K);

clk100:div10 port map (clk=>ca_1K,
                             outclk=>ca_100);

clk10:div10 port map (clk=>ca_100,
                             outclk=>ca_10 );
clk1:div10 port map (clk=>ca_10,
                             outclk=>ca_1 );

        outclk_1M<=ca_1M;
        outclk_100K<=ca_100K;
        outclk_10K <= ca_10K;
        outclk_1K <=ca_1K;
        outclk_100 <= ca_100;
        outclk_10 <=ca_10;
        outclk_1 <=ca_1;
end clkgen;