cpu16.vhd

一个16位cpu的vhdl代码。具体内容我也不清楚

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;  
 
entity cpu is
    port (
      DB:inout std_logic_vector(15 downto 0);
      AB:buffer std_logic_vector(15 downto 0);
      MUX: in std_logic_vector(0 to 2);
      CLKG,CLK,RESET,RUN: in std_logic;
      CI: buffer std_logic_vector(31 downto 0);
      CO: buffer std_logic_vector(31 downto 0);
      CWR,CRD,IOW,IOR,CTRL1,CTRL2,CTRL3,CTRL4,MCLK: buffer std_logic;
      PRIX,KRIX:in std_logic
    );
end cpu;


architecture cpu_arch of cpu is
signal ALOUT,ARIN,BXIN,SPOUT,SP2OUT,PCOUT,ADT,ADOUT: std_logic_vector(15 downto 0);
signal ADR,ADRIN,AR,BR,DIN,DOUT,IRX,DBX: std_logic_vector(15 downto 0);
signal SLMA,SLMB,SLAL:std_logic_vector(3 downto 0);
signal SLR,SLIM : std_logic_vector(3 downto 0);
signal SLMD : std_logic_vector(1 downto 0);
signal ADRG,SAI,SLMS,SLMP,ARG,BRG,CY,Z,N,V,DOTG,DOEN,DING: std_logic;
signal ADRGE,NADRG,DOTGE,DINGE,CN,WWR,MWR,MRD,ARGE,BRGE: std_logic;
signal SHCN: STD_LOGIC_VECTOR (3 downto 0);
signal SROR,SROL,SHRR,SASR,SLRN,CCK,ZCK,NCK,VCK,WSP,WPC,WLR: std_logic;
signal T: std_logic_vector(8 downto 0);
signal LOW2,LOW_INC: std_logic_vector(1 downto 0);
signal CA_W,CA_R,TAG_W,TAG_R : std_logic;			--come from CU    --L_MUX,
signal HIT : std_logic;
signal CA_DI, CA_DO : std_logic_vector(15 downto 0);
signal MUXIN : std_logic_vector(15 downto 0);		--选择从MEM还是 CACHE输入
signal COUNT: std_logic_vector(3 downto 0);
---------
signal STORE,LOAD: std_logic;


--alu----------------------------------------------------------------------------
component alu is
    Port (  ARIN : in std_logic_vector(15 downto 0);
            BXIN : in std_logic_vector(15 downto 0);
            SLAL : in std_logic_vector(3 downto 0);
            SLIM : in std_logic_vector(3 downto 0);
	    SLSH: in std_logic_vector(3 downto 0);
	    SROR,SROL,SHRR,SASR,SLRN: in std_logic;
            MCLK,CCK, NCK, ZCK,VCK,ARGE,BRGE :in std_logic;
            CY, N, Z, V :out std_logic;
            ALOUT : out std_logic_vector(15 downto 0) 
        );
end component;


--register-----------------------------------------------------------------------
component reg is
    port (
	DATA_in: in STD_LOGIC_VECTOR (15 downto 0) ;
	ADR_in,IR_in,DIN: in STD_LOGIC_VECTOR (15 downto 0) ;
	R_out1: out STD_LOGIC_VECTOR (15 downto 0) ;
	R_out2: out STD_LOGIC_VECTOR (15 downto 0) ;
	SPOUT,PCOUT: buffer STD_LOGIC_VECTOR(15 downto 0);
	MCLK,SLMS,SLMP: in STD_LOGIC;
	SLRW: in STD_LOGIC_VECTOR (3 downto 0) ;
	R_sel1: in STD_LOGIC_VECTOR (3 downto 0) ;
	R_sel2: in STD_LOGIC_VECTOR (3 downto 0) ;
	WSP,WPC,WLR,RESET: in STD_LOGIC;
	MUX: in STD_LOGIC_VECTOR(2 downto 0);
	TEST: buffer STD_LOGIC_VECTOR(31 downto 0)
	);
end component;


--control------------------------------------------------------------------------

component control is
    port (
        IR_in: in STD_LOGIC_VECTOR (15 downto 0);				--应该从CACHE来
	IRX: buffer STD_LOGIC_VECTOR (15 downto 0);
        SHRN: in STD_LOGIC_VECTOR(3 downto 0);					--移位位数在寄存器中，如ROR Rd,Rm
        CLK,CY,Z,N,V,RESET,RUN,MCLK : in std_logic;
        SLMD : out std_logic_vector(1 downto 0);
        SAI,ADRGE,WPC,WSP,WLR,DOTGE,DINGE: buffer std_logic;	--SAI控制选择PC，PC+2
	WWR,MWR,MRD: buffer std_logic;				--MEM读、写信号

        SLMA,SLMB,SLR: out STD_LOGIC_VECTOR (3 downto 0);
	SLMS,SLMP: out std_logic;
        SLAL: out STD_LOGIC_VECTOR (3 downto 0);
        SLIM: out std_logic_vector(3 downto 0);
        CCK,ZCK,NCK,VCK,ARGE,BRGE : out std_logic;
        SHCN: out STD_LOGIC_VECTOR (3 downto 0);
        SROR,SROL,SHRR,SASR,SLRN: out std_logic;

	--signals with cache--
	T: buffer std_logic_vector(8 downto 0);		--写M，读M，改地址，写C，判HIT/读C，执行，译码，取指
	CA_W: buffer std_logic;				--CACHE'写'信号
	TAG_W: buffer std_logic;			--TAG ‘写’信号
	TAG_R: buffer std_logic;
	CA_R: buffer std_logic;				--CACHE ‘读’, 用来控制透明锁存器	
--	L_MUX : out std_logic;				--CACHE MISS时，准备读一个BLOCK到MEM。
	HIT : in std_logic;
	LOW_INC: buffer std_logic_vector(1 downto 0);
---------
	STORE,LOAD: buffer std_logic;
	COUNT: buffer std_logic_vector(3 downto 0)

       );
end component;

----cache------------------------------------------------------------------------
component cache is
    Port (  ADR : in std_logic_vector(15 downto 0);
            CA_DI : inout std_logic_vector(15 downto 0);
	    CA_DO : inout std_logic_vector(15 downto 0);
	    HIT: out std_logic;
	    CA_W: in std_logic;				--CACHE'写'信号
	    TAG_W: in std_logic;			--TAG ‘写’信号
	    CA_R: in std_logic;				--CACHE ‘读’, 用来控制透明锁存器
	    TAG_R: in std_logic;
	    MCLK: in std_logic;
	    RST: in std_logic
        );
end component;

---------------------------------------------------------------------------------
   -- sizeIt replicates a value to an array of specific length.
   Function sizeIt(a: std_Logic; len: integer) return std_logic_vector is
      variable rep: std_logic_vector( len-1 downto 0);
   begin for i in rep'range loop rep(i) := a;  end loop; return rep;
   end sizeIt;

 constant TWO: std_logic_vector:="0000000000000010";

begin
	MCLK <= CLKG;

   alu1 : alu port map (  ARIN => ARIN, BXIN => BXIN,
            SLAL => SLAL, 
            SLIM => SLIM, SLSH => SHCN,
	    SROR => SROR,SROL => SROL,SHRR => SHRR,SASR => SASR,SLRN => SLRN,
            MCLK => MCLK, CCK => CCK, NCK=> NCK, ZCK => ZCK, VCK =>VCK,
            ARGE => ARGE, BRGE => BRGE,
	    CY => CY, N => N, Z => Z, V => V,
            ALOUT => ALOUT
            );
                        
     			
   registr :  reg port map ( 
	DATA_in => ALOUT,
	ADR_in => ADT,IR_in => IRX, DIN => DIN,
	R_out1 => ARIN,
	R_out2 => BXIN,
	SPOUT => SPOUT, PCOUT => PCOUT,
	MCLK => MCLK,SLMS=>SLMS, SLMP=>SLMP,
	SLRW => SLR,
	R_sel1 => SLMA, R_sel2 => SLMB,
	WSP => WSP, WPC => WPC, WLR => WLR, RESET => RESET,
	MUX => MUX, TEST => CI
    	);    	
		   
	ADOUT <= ADR when SLMD = "00" else
		SPOUT	when  SLMD = "01" else
		SP2OUT when  SLMD = "10" else
		PCOUT;
	ADRG <= MCLK and ADRGE;
	NADRG <= not ADRG;
	ADR <= (ALOUT and  SizeIt(ADRG, 16)) or (ADR and SizeIt(NADRG, 16));

	ADT <= ADOUT + TWO when SAI = '1' else ADOUT;

--送到MEM的地址
	AB(15 downto 3) <= ADOUT(15 downto 3);
	AB(0) <= ADOUT(0);
	AB(2 downto 1) <= LOW2;

	LOW2 <=	ADOUT(2 downto 1) when 
		T(0)='1' or
		T(5)='1' or
		(T(6)='1' and STORE='1') or
		(T(7)='1' and STORE='1' and HIT='1')
		else
  		LOW_INC;
	
	SP2OUT <= SPOUT - TWO;

--------加一个多路选择器，选择CA_DB还是DB和CPU相连。
	DOTG <= DOTGE;			--and MCLK;
	DOUT <= (BXIN and SizeIt(DOTG, 16)) or (DOUT and SizeIt(not DOTG, 16));

	DB <= DOUT when MWR = '0' else "ZZZZZZZZZZZZZZZZ";
	CA_DI <= DOUT when CA_W = '0' else "ZZZZZZZZZZZZZZZZ";

	DING <= DINGE;		--and MCLK;	
	MUXIN <= CA_DO when CA_R = '0' else 
		 DB;		 
	DBX <= "00000000000000" & PRIX & KRIX when (MRD = '0' and AB = "1000000000000100")
		else MUXIN;
	DIN <= (DBX and SizeIt(DING, 16)) or (DIN and SizeIt(not DING, 16));	
	
	CWR <= MWR or AB(15) or AB(0) or not MCLK;
	CTRL1 <= MWR or AB(15) or (not AB(0) and WWR) or not MCLK or not RUN;
	CRD <= MRD or AB(15) or not MCLK;

	IOW <= MWR or not AB(15) or not AB(1) or not MCLK; -- 8002H
	IOR <= MRD or not AB(15) or not AB(2) or not MCLK; -- 8004H

   cache1: cache port map(    
	ADR => AB,
        CA_DI => CA_DI,
	CA_DO => CA_DO,
	HIT => HIT,
	CA_W => CA_W,				--CACHE'写'信号
	TAG_W => TAG_W,				--TAG ‘写’信号
	CA_R => CA_R,				--CACHE ‘读’, 用来控制透明锁存器
	TAG_R => TAG_R,
	MCLK => MCLK,
	RST => RESET
        );

	        		       
   control1 : control port map( 
	IR_in => DIN,					--IR_out => IR,
	--
	IRX => IRX,
        SHRN => ARIN(3 downto 0),
        CLK => CLK, CY => CY, Z => Z, N => N, V => V,
	RESET => RESET, RUN => RUN, MCLK => MCLK,
        SLMD => SLMD,
        SAI => SAI, ADRGE => ADRGE, WPC => WPC, WSP => WSP, WLR => WLR,
	MWR => MWR, WWR => WWR,MRD => MRD, DOTGE => DOTGE, DINGE => DINGE,
        SLMA => SLMA, SLMB => SLMB, SLR => SLR,
	SLMS => SLMS, SLMP => SLMP,
        SLAL => SLAL,
        SLIM => SLIM,
        CCK => CCK, ZCK => ZCK, NCK => NCK, VCK => VCK,
	ARGE => ARGE, BRGE => BRGE,
        SHCN => SHCN,
        SROR => SROR,SROL => SROL,SHRR => SHRR,SASR => SASR,SLRN => SLRN,
	T => T,
	CA_W => CA_W,
	TAG_W => TAG_W,
	TAG_R => TAG_R,
	CA_R => CA_R,
	HIT => HIT,
	LOW_INC => LOW_INC,
	LOAD => LOAD,
	STORE => STORE,
	COUNT => COUNT
       );

--    CO(31 downto 28) <= SLR;
--    CO(27 downto 24) <= SLMA;
--    CO(23 downto 20) <= SLMB;
--    CO(19 downto 16) <= SLAL; 
    CO(31 downto 16) <= ADOUT;	
    CO(15 downto 12) <=	SLAL;		
    CO(11 downto 8) <= COUNT;
    CO(7 downto 6) <= LOW_INC;    
    CO(5) <= HIT;
    CO(4) <= T(7);
    CO(3) <= T(6);
    CO(2) <= T(5);
    CO(1) <= T(4);
    CO(0) <= T(0);
    CTRL2 <= T(1);		
    CTRL3 <= T(2);		
    CTRL4 <= T(3);		
 

end cpu_arch;