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📄 gray.inc

📁 ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.
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-- Copyright (C) 1991-1996 Altera Corporation-- Any megafunction design, and related net list (encrypted or decrypted),-- support information, device programming or simulation file, and any other-- associated documentation or information provided by Altera or a partner-- under Altera's Megafunction Partnership Program may be used only to-- program PLD devices (but not masked PLD devices) from Altera.  Any other-- use of such megafunction design, net list, support information, device-- programming or simulation file, or any other related documentation or-- information is prohibited for any other purpose, including, but not-- limited to modification, reverse engineering, de-compiling, or use with-- any other silicon devices, unless such use is explicitly licensed under-- a separate agreement with Altera or a megafunction partner.  Title to-- the intellectual property, including patents, copyrights, trademarks,-- trade secrets, or maskworks, embodied in any such megafunction design,-- net list, support information, device programming or simulation file, or-- any other related documentation or information provided by Altera or a-- megafunction partner, remains with Altera, the megafunction partner, or-- their respective licensors.  No other licenses, including any licenses-- needed under any third party's intellectual property, are provided herein.-- MAX+plus II Include File-- Version 7.1 11/22/96-- Created: Wed Apr 23 14:32:08 1997FUNCTION gray (clock, cnt_en, aclr)    WITH (LPM_WIDTH, DEVICE_FAMILY, CARRY_CHAIN, CARRY_CHAIN_LENGTH)    RETURNS (q[(lpm_width) - (1)..0]);

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