mot_mux.tdf

ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.

TITLE "Adress multiplexer for MOTOROLA 68030 CPU" ;
-- Version 1.0, 13.11.1997
-- Copyright Frank Rodler

PARAMETERS
(
   ADR_WIDTH = 20
) ;

CONSTANT ADR_HALF_1 = CEIL(ADR_WIDTH DIV 2) ;
CONSTANT ADR_HALF_2 = FLOOR(ADR_WIDTH DIV 2) ;

SUBDESIGN mot_mux     -- That's our interface name to the rest of the world
(
   clk                 : INPUT ;
   A0                  : INPUT ;
   A1                  : INPUT ;
   SIZ0                : INPUT ;
   SIZ1                : INPUT ;
   ADRin[ADR_WIDTH-1..0] : INPUT ;
   RnW                 : INPUT ;
   CS                  : INPUT ;
   AdMux0              : INPUT ;
   AdMux1              : INPUT ;
   rc_mux              : INPUT ;

   Wout[3..0]          : OUTPUT ;  -- to dynram module
   Rout                : OUTPUT ;  -- to dynram module
   CSout               : OUTPUT ;  -- to dynram module
   A_DRAM[((ADR_WIDTH DIV 2)-1)..0] : OUTPUT ;  -- directy to DRAM chips (via 33 Ohm)
)

VARIABLE		           -- I tell the compiler what staff I want to use

  hi[ADR_HALF_1-1..0] : node ;
  lo[ADR_HALF_2-1..0] : node ;
  A_DRAM[ADR_HALF_1-1..0] : DFF ;

BEGIN

ASSERT (ADR_HALF_1 == ADR_HALF_2)
REPORT "Error: ADR_WIDTH (%) must be an even number" ADR_WIDTH 
  SEVERITY ERROR ;

hi[] = ADRin[ADR_WIDTH-1..ADR_HALF_1] ;
lo[] = ADRin[ADR_HALF_1-1..0] ;

A_DRAM[].clk = clk ;
IF (AdMux0 & !AdMux1 & rc_mux) THEN
  A_DRAM[].d = hi[] ;
ELSIF (AdMux0 & AdMux1 & rc_mux) THEN
  A_DRAM[].d = lo[] ;
ELSE 
  A_DRAM[].d = A_DRAM[].q ;
END IF ;
 
TABLE
   SIZ1, SIZ0, A1, A0, RnW, CS  =>   Wout[], Rout, CSout ;
     X ,   X ,  X,  X,  X ,  1  =>  B"1111",   1 ,    1  ;

     0 ,   1 ,  0,  0,  0 ,  0  =>  B"1110",   1 ,    0  ;
     0 ,   1 ,  0,  1,  0 ,  0  =>  B"1101",   1 ,    0  ;
     0 ,   1 ,  1,  0,  0 ,  0  =>  B"1011",   1 ,    0  ;
     0 ,   1 ,  1,  1,  0 ,  0  =>  B"0111",   1 ,    0  ;

     1 ,   0 ,  0,  0,  0 ,  0  =>  B"1100",   1 ,    0  ;
     1 ,   0 ,  0,  1,  0 ,  0  =>  B"1001",   1 ,    0  ;
     1 ,   0 ,  1,  0,  0 ,  0  =>  B"0011",   1 ,    0  ;
     1 ,   0 ,  1,  1,  0 ,  0  =>  B"0111",   1 ,    0  ;

     1 ,   1 ,  0,  0,  0 ,  0  =>  B"1000",   1 ,    0  ;
     1 ,   1 ,  0,  1,  0 ,  0  =>  B"0001",   1 ,    0  ;
     1 ,   1 ,  1,  0,  0 ,  0  =>  B"0011",   1 ,    0  ;
     1 ,   1 ,  1,  1,  0 ,  0  =>  B"0111",   1 ,    0  ;

     0 ,   0 ,  0,  0,  0 ,  0  =>  B"0000",   1 ,    0  ;
     0 ,   0 ,  0,  1,  0 ,  0  =>  B"0001",   1 ,    0  ;
     0 ,   0 ,  1,  0,  0 ,  0  =>  B"0011",   1 ,    0  ;
     0 ,   0 ,  1,  1,  0 ,  0  =>  B"0111",   1 ,    0  ;

     X ,   X ,  X,  X,  1 ,  0  =>  B"1111",   0 ,    0  ;
END TABLE ;

END ;